AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

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Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA Design Flow for AMD* Xilinx* Users 2. Technology Comparison 3. FPGA Tools Comparison 4. AMD* Xilinx* to Intel® FPGA Design Conversion 5. Conclusion 6. AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users Archives 7. Document Revision History for Intel® FPGA Design Flow for AMD* Xilinx* Users
2. Technology Comparison x
2.1. Intel® FPGA and SoC Devices 2.2. Intel® - AMD* Xilinx* Device Comparison 2.3. Intel® FPGA Device Features
3. FPGA Tools Comparison x
3.1. Hardware and Software Tools for FPGA Design 3.2. FPGA Design Flow Using Command Line Scripting 3.3. FPGA Design Flow Using Tools with GUIs 3.4. Additional Quartus® Prime Pro Edition Features
3.2. FPGA Design Flow Using Command Line Scripting x
3.2.1. Command-Line Executable Equivalents 3.2.2. Programming and Configuration File Support in the Quartus® Prime Pro Edition Software
3.2.1. Command-Line Executable Equivalents x
3.2.1.1. synth_design 3.2.1.2. place_design/route_design 3.2.1.3. report_timing 3.2.1.4. write_bitstream 3.2.1.5. write_sdf/write_verilog/write_vhdl 3.2.1.6. report_power 3.2.1.7. write_checkpoint 3.2.1.8. Run Complete Design Flow
3.3. FPGA Design Flow Using Tools with GUIs x
3.3.1. Project Creation 3.3.2. Design Entry 3.3.3. IP Status 3.3.4. Design Constraints 3.3.5. Synthesis 3.3.6. Design Implementation 3.3.7. Finalize Pinout 3.3.8. Viewing and Editing Design Placement 3.3.9. Static Timing Analysis 3.3.10. Generation of Device Programming Files 3.3.11. Power Analysis 3.3.12. Simulation 3.3.13. Hardware Verification 3.3.14. View Netlist 3.3.15. Design Optimization 3.3.16. Techniques to Improve Productivity 3.3.17. Partial Reconfiguration 3.3.18. Cross-Probing in the Quartus® Prime Pro Edition Software
3.3.2. Design Entry x
3.3.2.1. HDL Editor 3.3.2.2. Schematic/Block Editor 3.3.2.3. State Machine Editor 3.3.2.4. IP Catalog and Parameter Editor 3.3.2.5. Platform Designer System Integration Tool 3.3.2.6. Platform Designer Component Editor
3.3.4. Design Constraints x
3.3.4.1. Assignment Editor 3.3.4.2. Create Timing Constraints with the Timing Analyzer GUI 3.3.4.3. Create Timing Constraints with the Timing Analyzer Text Editor
3.3.7. Finalize Pinout x
3.3.7.1. Pin Planner 3.3.7.2. Interface Planner 3.3.7.3. Tile Interface Planner
3.3.12. Simulation x
3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores
3.3.13. Hardware Verification x
3.3.13.1. System Console 3.3.13.2. Signal Tap Logic Analyzer 3.3.13.3. In-System Sources and Probes 3.3.13.4. Toolkit Explorer 3.3.13.5. Remote Debugging 3.3.13.6. Other Intel® FPGA Debugging Tools
3.3.13.4. Toolkit Explorer x
3.3.13.4.1. Transceiver Toolkit 3.3.13.4.2. EMIF Debug Toolkit
3.3.14. View Netlist x
3.3.14.1. RTL Viewer 3.3.14.2. Technology Map Viewer
3.3.15. Design Optimization x
3.3.15.1. Hyper-Aware Design Flow 3.3.15.2. Physical Synthesis Optimization 3.3.15.3. Optimization Modes 3.3.15.4. Fractal Synthesis
3.3.16. Techniques to Improve Productivity x
3.3.16.1. Fast Preservation 3.3.16.2. Engineering Change Order (ECO) Flow 3.3.16.3. Block-Based Design Flow 3.3.16.4. Design Assistant 3.3.16.5. Snapshot Viewer 3.3.16.6. Design Space Explorer II
3.4. Additional Quartus® Prime Pro Edition Features x
3.4.1. Scripting with Tcl in the Quartus® Prime Pro Edition Software
3.4.1. Scripting with Tcl in the Quartus® Prime Pro Edition Software x
3.4.1.1. Running Scripts from the DOS or UNIX Prompt 3.4.1.2. Running Scripts in Batch Mode from a Shell 3.4.1.3. Running Tcl Commands Directly from the Command Line 3.4.1.4. Running Tcl Commands Interactively from the Shell 3.4.1.5. The Quartus® Prime Tcl Console Window
4. AMD* Xilinx* to Intel® FPGA Design Conversion x
4.1. Replacing AMD* Xilinx* Primitives 4.2. Converting IP Cores 4.3. Setting Equivalent AMD* Xilinx* Design Constraints 4.4. Setting Up the Simulation Environment
4.1. Replacing AMD* Xilinx* Primitives x
4.1.1. Converting I/O Buffers 4.1.2. Changing Default I/O Standard for Pins 4.1.3. Converting Registers
4.1.1. Converting I/O Buffers x
4.1.1.1. Example of Converting I/O Buffer
4.2. Converting IP Cores x
4.2.1. Converting Memory Blocks 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) 4.2.3. Converting Multipliers
4.2.1. Converting Memory Blocks x
4.2.1.1. Embedded Memory Blocks 4.2.1.2. Differences Between AMD* Xilinx* Memory and Intel® FPGA Memory 4.2.1.3. Determining Memory Block and Mapping Ports 4.2.1.4. Memory Port Mapping 4.2.1.5. Example: Converting Simple Dual-Port RAM
4.2.1.2. Differences Between AMD* Xilinx* Memory and Intel® FPGA Memory x
4.2.1.2.1. Memory Mode 4.2.1.2.2. Clocking Mode 4.2.1.2.3. Write and Read Operation Triggering 4.2.1.2.4. Read-During-Write Operation at the Same Address 4.2.1.2.5. Error Correction Code (ECC) 4.2.1.2.6. Byte Enable 4.2.1.2.7. Address Clock Enable 4.2.1.2.8. Parity Bit Support 4.2.1.2.9. Memory Initialization 4.2.1.2.10. Output Synchronous Set/Reset
4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) x
4.2.2.1. Feature Comparison 4.2.2.2. Port Mapping Reference 4.2.2.3. Example: Converting AMD* Xilinx* MMCM into an Intel® PLL
4.2.3. Converting Multipliers x
4.2.3.1. Feature Comparison 4.2.3.2. Port Mapping 4.2.3.3. Example: Converting to the LPM_MULT IP Core 4.2.3.4. Example: Converting to the Intel® FPGA Multiply Adder IP core
4.3. Setting Equivalent AMD* Xilinx* Design Constraints x
4.3.1. Device Constraints 4.3.2. Placement Constraints 4.3.3. Timing Constraints 4.3.4. Retimer Constraints
4.3.1. Device Constraints x
4.3.1.1. DRIVE 4.3.1.2. SLEW 4.3.1.3. IOB 4.3.1.4. IOSTANDARD 4.3.1.5. KEEP
4.3.2. Placement Constraints x
4.3.2.1. PBLOCK 4.3.2.2. PACKAGE_PIN 4.3.2.3. LOC & BEL 4.3.2.4. PROHIBIT
4.3.2.1. PBLOCK x
4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions
4.3.3. Timing Constraints x
4.3.3.1. Clock Domain Crossing
4.4. Setting Up the Simulation Environment x
4.4.1. Simulation Levels 4.4.2. HDL Support for EDA Simulators 4.4.3. Value Change Dump (VCD) Support 4.4.4. Simulating Intel FPGA IP Cores
1. Introduction to Intel® FPGA Design Flow for AMD* Xilinx* Users
2. Technology Comparison
3. FPGA Tools Comparison
4. AMD* Xilinx* to Intel® FPGA Design Conversion
5. Conclusion
6. AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users Archives
7. Document Revision History for Intel® FPGA Design Flow for AMD* Xilinx* Users

4.2.1.4. Memory Port Mapping

The following table lists the memory ports that the Vivado* ’s IP Catalog generates, and their corresponding mapping to Intel® FPGA memory ports for different memory modes.

Table 49.  Block Memory Generator's Memory Port Mapping to Intel® FPGA Memory Ports
Port Description AMD* Xilinx* Ports Port-Mapping to Intel® FPGA Ports in Different Memory Modes
Single-Port RAM Simple Dual-Port RAM True Dual-Port RAM Single-Port ROM Dual-Port ROM
Port A: address addra address wraddress wraddress/ address_a address address_a
Port A: data input dina data data data/ data_a — —
Port A: parity data input dinpa —
Port A: clock enable for the input register ena inclocken/ clken inclocken/ wrclocken/ enable inclocken/ wrclocken/ enable inclocken/ clken enable
Port A: clock enable for the last output register regcea, ena outclocken/ clken enable outclocken/ enable outclocken/clken enable
Port A: write enable NA wren wren wren/ wren_a NA NA
Port A: byte enable19 wea byteena byteena_a byteena_a NA NA
Port A: asynchronous clear NA outaclr/ aclr NA out_aclr/ rd_aclr/ aclr outaclr/aclr aclr
Port A: synchronous set/reset rsta/ rstrega sclr NA sclr sclr sclr
Port A: read enable ena (in SDP 20 mode) rden NA rden_a/ rden rden rden_a
Port A: in clock clka inclock/ clock inclock/ wrclock/ clock inclock/ wrclock/ clock inclock/ clock clock
Port A: out clock NA outclock/ clock NA NA outclock/ clock NA
Port A: data output douta q NA q/ q_a q q_a
Port A: parity data output doutpa —
Port A: address enable addrena 21 addressstall_a wr_addressstall wr_addressstall/ addressstall_a addressstall_a addressstall_a
Port B: address addrb NA rdaddress rdaddress/ address_b NA address_b
Port B: data input dinb NA NA data_b NA NA
Port B: parity data input dinpb —
Port B: clock enable for the input register enb NA NA inclocken/enable NA enable
Port B: clock enable for the last output register regceb, enb NA outclocken/ rdoutclocken outclocken/enable NA enable
Port B: write enable enb (in SDP20 mode) NA NA wren_b NA NA
Port B: byte enable web NA NA byteena_b NA NA
Port B: asynchronous clear — NA out_aclr/ rd_aclr/ aclr rd_aclr/ out_aclr NA aclr
Port B: synchronous set/reset rstb/ rstregb NA sclr sclr NA sclr
Port B: read enable — NA rden rden_b NA rden_b
Port B: clock clkb outclock/ clock outclock/ rdclock/ clock outclock/ rdclock outclock/ clock clock
Port B: data output doutb NA q q/ q_b NA q_b
Port B: address enable addrenb NA rd_addressstall rd_addressstall/ addressstall_b NA addressstall_b
Port B: parity data output doutpb —
Single bit error sbiterr NA eccstatus[1:0] NA NA NA
Double bit error dbiterr NA NA NA NA
ECC encoder bypass port ‒ NA eccencbypass NA NA NA
ECC parity flip port ‒ NA eccncparity[7:0] NA NA NA
Inject single bit error injectsberr NA
Inject double bit error injectdbiterr NA

You can also infer RAM in HDL. For more information, refer to the Recommended HDL Coding Styles in Quartus® Prime Pro Edition User Guide: Design Recommendations.

Related Information
19 For configurations less that two bytes wide, AMD* Xilinx* write enable signals (wea and web) are equivalent to Intel® FPGA write enable signals (wren, wren_a, or wren_b) signals, depending on the memory mode used. For configurations of more than two bytes, AMD* Xilinx* 's write enable buses (wea[] and web[]) are equivalent to Intel® FPGA byte enable buses(byteena[], byteena_a[], or byteena_b[]), depending on the memory mode used. Also, the Intel® FPGA write enable signal needs to be asserted for the write operation.
20 AMD* Xilinx* simple dual-port RAM generated through Block Memory Generator
21 Port mappings denoted with NA are not applicable for that memory mode; port-mappings denoted with — are not supported in Intel® FPGA memory.
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