AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

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ID 683562
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® FPGA Design Flow for AMD* Xilinx* Users 2. Technology Comparison 3. FPGA Tools Comparison 4. AMD* Xilinx* to Intel® FPGA Design Conversion 5. Conclusion 6. AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users Archives 7. Document Revision History for Intel® FPGA Design Flow for AMD* Xilinx* Users
2. Technology Comparison x
2.1. Intel® FPGA and SoC Devices 2.2. Intel® - AMD* Xilinx* Device Comparison 2.3. Intel® FPGA Device Features
3. FPGA Tools Comparison x
3.1. Hardware and Software Tools for FPGA Design 3.2. FPGA Design Flow Using Command Line Scripting 3.3. FPGA Design Flow Using Tools with GUIs 3.4. Additional Quartus® Prime Pro Edition Features
3.2. FPGA Design Flow Using Command Line Scripting x
3.2.1. Command-Line Executable Equivalents 3.2.2. Programming and Configuration File Support in the Quartus® Prime Pro Edition Software
3.2.1. Command-Line Executable Equivalents x
3.2.1.1. synth_design 3.2.1.2. place_design/route_design 3.2.1.3. report_timing 3.2.1.4. write_bitstream 3.2.1.5. write_sdf/write_verilog/write_vhdl 3.2.1.6. report_power 3.2.1.7. write_checkpoint 3.2.1.8. Run Complete Design Flow
3.3. FPGA Design Flow Using Tools with GUIs x
3.3.1. Project Creation 3.3.2. Design Entry 3.3.3. IP Status 3.3.4. Design Constraints 3.3.5. Synthesis 3.3.6. Design Implementation 3.3.7. Finalize Pinout 3.3.8. Viewing and Editing Design Placement 3.3.9. Static Timing Analysis 3.3.10. Generation of Device Programming Files 3.3.11. Power Analysis 3.3.12. Simulation 3.3.13. Hardware Verification 3.3.14. View Netlist 3.3.15. Design Optimization 3.3.16. Techniques to Improve Productivity 3.3.17. Partial Reconfiguration 3.3.18. Cross-Probing in the Quartus® Prime Pro Edition Software
3.3.2. Design Entry x
3.3.2.1. HDL Editor 3.3.2.2. Schematic/Block Editor 3.3.2.3. State Machine Editor 3.3.2.4. IP Catalog and Parameter Editor 3.3.2.5. Platform Designer System Integration Tool 3.3.2.6. Platform Designer Component Editor
3.3.4. Design Constraints x
3.3.4.1. Assignment Editor 3.3.4.2. Create Timing Constraints with the Timing Analyzer GUI 3.3.4.3. Create Timing Constraints with the Timing Analyzer Text Editor
3.3.7. Finalize Pinout x
3.3.7.1. Pin Planner 3.3.7.2. Interface Planner 3.3.7.3. Tile Interface Planner
3.3.12. Simulation x
3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores
3.3.13. Hardware Verification x
3.3.13.1. System Console 3.3.13.2. Signal Tap Logic Analyzer 3.3.13.3. In-System Sources and Probes 3.3.13.4. Toolkit Explorer 3.3.13.5. Remote Debugging 3.3.13.6. Other Intel® FPGA Debugging Tools
3.3.13.4. Toolkit Explorer x
3.3.13.4.1. Transceiver Toolkit 3.3.13.4.2. EMIF Debug Toolkit
3.3.14. View Netlist x
3.3.14.1. RTL Viewer 3.3.14.2. Technology Map Viewer
3.3.15. Design Optimization x
3.3.15.1. Hyper-Aware Design Flow 3.3.15.2. Physical Synthesis Optimization 3.3.15.3. Optimization Modes 3.3.15.4. Fractal Synthesis
3.3.16. Techniques to Improve Productivity x
3.3.16.1. Fast Preservation 3.3.16.2. Engineering Change Order (ECO) Flow 3.3.16.3. Block-Based Design Flow 3.3.16.4. Design Assistant 3.3.16.5. Snapshot Viewer 3.3.16.6. Design Space Explorer II
3.4. Additional Quartus® Prime Pro Edition Features x
3.4.1. Scripting with Tcl in the Quartus® Prime Pro Edition Software
3.4.1. Scripting with Tcl in the Quartus® Prime Pro Edition Software x
3.4.1.1. Running Scripts from the DOS or UNIX Prompt 3.4.1.2. Running Scripts in Batch Mode from a Shell 3.4.1.3. Running Tcl Commands Directly from the Command Line 3.4.1.4. Running Tcl Commands Interactively from the Shell 3.4.1.5. The Quartus® Prime Tcl Console Window
4. AMD* Xilinx* to Intel® FPGA Design Conversion x
4.1. Replacing AMD* Xilinx* Primitives 4.2. Converting IP Cores 4.3. Setting Equivalent AMD* Xilinx* Design Constraints 4.4. Setting Up the Simulation Environment
4.1. Replacing AMD* Xilinx* Primitives x
4.1.1. Converting I/O Buffers 4.1.2. Changing Default I/O Standard for Pins 4.1.3. Converting Registers
4.1.1. Converting I/O Buffers x
4.1.1.1. Example of Converting I/O Buffer
4.2. Converting IP Cores x
4.2.1. Converting Memory Blocks 4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) 4.2.3. Converting Multipliers
4.2.1. Converting Memory Blocks x
4.2.1.1. Embedded Memory Blocks 4.2.1.2. Differences Between AMD* Xilinx* Memory and Intel® FPGA Memory 4.2.1.3. Determining Memory Block and Mapping Ports 4.2.1.4. Memory Port Mapping 4.2.1.5. Example: Converting Simple Dual-Port RAM
4.2.1.2. Differences Between AMD* Xilinx* Memory and Intel® FPGA Memory x
4.2.1.2.1. Memory Mode 4.2.1.2.2. Clocking Mode 4.2.1.2.3. Write and Read Operation Triggering 4.2.1.2.4. Read-During-Write Operation at the Same Address 4.2.1.2.5. Error Correction Code (ECC) 4.2.1.2.6. Byte Enable 4.2.1.2.7. Address Clock Enable 4.2.1.2.8. Parity Bit Support 4.2.1.2.9. Memory Initialization 4.2.1.2.10. Output Synchronous Set/Reset
4.2.2. Converting Mixed-Mode Clock Manager (MMCM) to Phase-Locked Loop (PLL) x
4.2.2.1. Feature Comparison 4.2.2.2. Port Mapping Reference 4.2.2.3. Example: Converting AMD* Xilinx* MMCM into an Intel® PLL
4.2.3. Converting Multipliers x
4.2.3.1. Feature Comparison 4.2.3.2. Port Mapping 4.2.3.3. Example: Converting to the LPM_MULT IP Core 4.2.3.4. Example: Converting to the Intel® FPGA Multiply Adder IP core
4.3. Setting Equivalent AMD* Xilinx* Design Constraints x
4.3.1. Device Constraints 4.3.2. Placement Constraints 4.3.3. Timing Constraints 4.3.4. Retimer Constraints
4.3.1. Device Constraints x
4.3.1.1. DRIVE 4.3.1.2. SLEW 4.3.1.3. IOB 4.3.1.4. IOSTANDARD 4.3.1.5. KEEP
4.3.2. Placement Constraints x
4.3.2.1. PBLOCK 4.3.2.2. PACKAGE_PIN 4.3.2.3. LOC & BEL 4.3.2.4. PROHIBIT
4.3.2.1. PBLOCK x
4.3.2.1.1. Differences Between PBLOCK and Logic Lock Regions
4.3.3. Timing Constraints x
4.3.3.1. Clock Domain Crossing
4.4. Setting Up the Simulation Environment x
4.4.1. Simulation Levels 4.4.2. HDL Support for EDA Simulators 4.4.3. Value Change Dump (VCD) Support 4.4.4. Simulating Intel FPGA IP Cores
1. Introduction to Intel® FPGA Design Flow for AMD* Xilinx* Users
2. Technology Comparison
3. FPGA Tools Comparison
4. AMD* Xilinx* to Intel® FPGA Design Conversion
5. Conclusion
6. AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users Archives
7. Document Revision History for Intel® FPGA Design Flow for AMD* Xilinx* Users

3.3. FPGA Design Flow Using Tools with GUIs

The Quartus® Prime Pro Edition and the Vivado* software GUIs address the major FPGA design steps in different ways.

Table 9.  GUI Feature Equivalents
GUI Feature AMD* Xilinx* Vivado* Software Quartus® Prime Pro Edition Software
Project Creation New Project New Project Wizard
Design Entry HDL Editor HDL Editor
EDA Netlist EDA Netlist
- Schematic/Block Editor
- State Machine Editor
- State Machine Viewer
IP Catalog IP Catalog and Parameter Editor
IP Integrator Platform Designer System Integration Tool
IP Packager Platform Designer Component Editor
IP Status Report IP Status Upgrade IP Components
Design Constraints Device, Physical and Timing Constraints window

Assignment Editor,

Timing Analyzer Text Editor

Synthesis Synthesis Analysis and Synthesis
Third-Party EDA Synthesis Third-Party EDA Synthesis
Design Implementation Implementation Fitter (Plan, Place, Route, Retime0 and Finalize)
Finalize Pinout

Byte Planner for memory banks

Device Window and Package Window in I/O Planning View Layout

Interface Planner

Tile Interface Planner

Pin Planner
Viewing and Editing Design Placement

Device Window (in I/O Planner View Layout)

Package Window (in I/O Planner View Layout)

 Chip Planner
Static Timing Analysis Report Timing Timing Analyzer
Generation of Device Programming Files Hardware Manager Assembler
Power Analysis

AMD* Xilinx* Power Estimator (XPE)

Report Power

Power and Thermal Calculator (PTC)

Early Power Estimation (EPE)

Power Analyzer
Simulation Vivado* Simulator

Questa* Intel® FPGA Starter Edition

Third-Party Simulation Tools Third-Party Simulation Tools
Hardware verification Hardware Manager System Console
Integrated Logic Analyzer (ILA) and System ILA IP Signal Tap Logic Analyzer
AMD* Xilinx* Virtual Input Output (VIO) In-System Sources and Probes
JTAG-to-AXI Master System Console
IBERT IP and Serial I/O Analyzer Tool Transceiver Toolkit
Memory Calibration Debug Tool

EMIF Debug Toolkit

EMIF Debug GUI
Remote Debug using AMD* Xilinx* Virtual Cable (XVC) Remote Debug using existing TCP/IP connection
-

Signal Probe

In-System Memory Content Editor

Logic Analyzer Interface (LAI)
View Netlist

Schematic Window (Elaborated)

Schematic Window (Synthesized)

Schematic Window (Implemented)

RTL Viewer (Post Synthesis)

Technology Map Viewer (Post-Mapping)

Technology Map Viewer (Post-Fitting)

Fast Forward Viewer (Post-Fitting)
Design Optimization - Hyper-Aware Design Flow10
Physical Optimization Physical Synthesis Optimization
Techniques to improve productivity Incremental Compile Block-Based Design Flows
Hierarchical Design
- Design Space Explorer II (DSE)
Design Rule Checking Design Assistant
Intermediate Design Snapshot Viewer
Partial Reconfiguration Yes Yes
Output Products Design Checkpoints Export Design Partitions
Add-On Development Tools Vivado* High-Level Synthesis High-Level Synthesis Compiler

 


Section Content
Project Creation
Design Entry
IP Status
Design Constraints
Synthesis
Design Implementation
Finalize Pinout
Viewing and Editing Design Placement
Static Timing Analysis
Generation of Device Programming Files
Power Analysis
Simulation
Hardware Verification
View Netlist
Design Optimization
Techniques to Improve Productivity
Partial Reconfiguration
Cross-Probing in the Quartus Prime Pro Edition Software

10 Hyper-Aware Design Flow available only for Stratix® 10 devices.
Level Two Title