Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

ID 683552
Date 9/24/2018
Public
Document Table of Contents

3.3.2.2. PRBS Signal Eye Test Configuration ( Stratix® V)

Use the following configuration to perform PRBS signal eye testing in Stratix® V designs.
PRBS Signal Eye Test Configuration ( Stratix® V)


System Connections: PRBS Signal Eye Tests ( Stratix® V)
From To

Your Design Logic

Data Pattern Generator bypass port

Data Pattern Generator

PHY input port

JTAG to Avalon® Master Bridge

Intel Avalon® Data Pattern Generator

JTAG to Avalon® Master Bridge

Intel Avalon® Data Pattern Checker

Data Pattern Checker

PHY output port

JTAG to Avalon® Master Bridge

Transceiver Reconfiguration Controller

JTAG to Avalon® Master Bridge

PHY input port

Transceiver Reconfiguration Controller

PHY input port

Enabling Serial Bit Comparator Mode ( Stratix V)

Serial bit comparator mode allows you to run Eye Viewer diagnostic features with any PRBS patterns or user-design data, without disrupting the data path. For Stratix® V devices, you must enable Serial bit comparator mode.

To enable this mode for Stratix® V devices, you must enable the following debugging component options when configuring the debugging system:

Table 37.  Component Settings for Serial Bit Comparator Mode
Debugging Component Setting for Serial Bit Mode2
Transceiver Reconfiguration Controller Turn on Enable Eye Viewer block and Enable Bit Error Rate Block
Data Pattern Generator3 Turn on Enable Bypass interface

Serial bit comparator mode is less accurate than Data pattern checker mode for single bit error checking. Do not use Serial bit comparator mode if you require an exact error rate. Use the Serial bit comparator mode for checking a large window of error. The toolkit does not read the bit error counter in real-time because it reads through the memory-mapped interface. Serial bit comparator mode has the following hardware limitations for Stratix® V devices:

  • Toolkit uses serial bit checker only on a single channel per reconfiguration controller at a time.
  • When the serial bit checker is running on channel n, you can change only the VOD, pre-emphasis, DC gain, and Eye Viewer settings on that channel. Changing or enabling DFE or CTLE can cause corruption of the serial bit checker results.
  • When the serial bit checker is running on a channel, you cannot change settings on any other channel on the same reconfiguration controller.
  • When the serial bit checker is running on a channel, you cannot open any other channel in the Transceiver Toolkit.
  • When the serial bit checker is running on a channel, you cannot copy PMA settings from any channel on the same reconfiguration controller.
2 Settings in Table 37 are supported in Stratix® V devices only.
3 Limited support for Data Pattern Generator or data pattern in Serial Bit Mode.