AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.2.2. Synchronous Reset Design Strategies

The use of synchronous resets helps to ensure a fully synchronous design. The Intel® Quartus® Prime Timing Analyzer can more efficiently analyze synchronous designs.

If you use an asynchronous reset source, synchronize the source before feeding it to the register's reset input. Depending on the design specifications, you can externally synchronize the reset source. Whether you synchronize the reset source internally or externally, it is part of the data logic path. Hence, you can easily determine the data arrival and data required times for proper slack analysis.

Like any broadcast signal, a synchronous reset has a high fan-out. The high fan-out makes it difficult (and at times impossible) to close timing without pipelining and duplicating the synchronous reset source.

A good technique for synchronous reset is to build a balanced reset tree, as Figure 5 shows. In this example, srstb_main output of the reset synchronizer serves as the main source of the distributed synchronous reset tree. The reduction of fan-out at each stage can ease the delay paths passed through by each reset branch, thereby helping to close timing.

Figure 5.  srstb_main as Synchronous Reset Source

You can use Hyper-Pipelining and Hyper-Retiming in your design to generate a similar reset distribution. The main goal of this design technique is to address the critical paths connecting the synchronous reset line. The Fitter accomplishes this by moving the registers on the pipeline and retiming them as needed to resolve timing issues.

Another design technique to reduce fan-out involves specifying the DUPLICATE_HIERARCHY_DEPTH assignment in the Intel® Quartus® Prime settings file (.qsf). This assignment can distribute duplicate registers of any high fan-out broadcast signals using hierarchical proximity to guide the duplication process.

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