AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.3.1. Example: Asynchronous Reset Design Assistant Analysis

You can use Design Assistant to identify and correct problematic asynchronous reset conditions. For this example, Figure 6 shows a circuit with two separate groups of registers, with asynchronous resets driven by the input port rstb.

Figure 6. Circuit Design with Asynchronous Reset

The following steps describe Design Assistant reset analysis of the circuit:

  1. After running the Fitter or a full compilation, view the Design Assistant reports in the Timing Analyzer report folder of the Compilation Report.
    Figure 7. Design Assistant Report in Timing Analyzer Folder of Compilation Report
  2. Review any rule violations in the report. This example shows 20 violations of rule RES-50001 – Asynchronous Resets Not Synchronized. Select RES-50001 in the list to show all instances violating the specific rule in your design.
    Figure 8. Design Assistant (Signoff) Results
  3. Find the location of rule violations in your design. You can cross probe each instance to locate the node.
    Figure 9. Locating to RES-50001 Rule Violations
  4. Identify the root cause of the violation and the recommendation for correction in the Design Assistant Recommendation.
    Figure 10. RES-50001 Rule Recommendation
  5. Implement the rule Recommendation in your design RTL. In this example, Design Assistant recommends inserting a synchronizer to feed all asynchronous reset pins the report specifies, as the following example shows.
    Note: To time the recovery and removal going to the reset pin, the clock domain of the synchronizer must match the latching domain of the register being reset.
    Figure 11. Adding a VDD-Based Reset Synchronizer
  6. Recompile the design with your changes, and rerun Design Assistant to confirm corrections. Repeat steps 1 through 6 until all issues are fixed.
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