AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.2.1. Asynchronous Reset Design Strategies

The primary disadvantage of using an asynchronous reset is that the reset is asynchronous both at the assertion and de-assertion of the signal.

The signal assertion is not the problem on the actual connected flip-flop. Even if the flip-flop moves to a metastable state, the flip-flop remains unstable only for a short period of time after assertion. After reset asserts long enough, all registers eventually settle to a reset state.

The problem of the asynchronous reset involves the signal de-assertion. If an asynchronous reset releases at or near the active clock edge, the output of the flip-flop could go to a metastable state, violating the reset recovery time of the flip-flop. The flip-flop then goes to an unknown state that can cause unexpected results upon entering normal operation.

You can insert a synchronously de-asserted reset circuit to prevent this condition. Synchronization of the reset signal on a specific clock domain requires a minimum of two flops. Figure 1 shows the first flip-flop (FF1) with output Q reset to 0, and input D tied high. This flip-flop can go to a metastable state if RSTB is de-asserted near a CLK active edge. However, the second flip-flop (FF2) remains stable at 0, since the input and output are both low, preventing any output change due to the input that might occur when a reset is removed.

Figure 1. VDD-based Reset Synchronizer

Using the VDD-based reset synchronizer, you can generate the main source (arstb_main) for the asynchronous reset. The reset is typically a high fan-out net. Implement a reset tree to maintain a good fan-out load to help meet the recovery and removal checks on driven registers during de-assertion. Figure 2 shows how arstb_main is distributed to drive the asynchronous resets of the registers.

Figure 2.  arstb_main as Asynchronous Reset Source
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