AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry

After correcting the asynchronous related issues in the reset circuitry for this example, Design Assistant reports two violations for the two new registers because rstb drives their asynchronous reset pins. However, the rstb clock domain is unrelated or asynchronous to the latching domain of the register.
Figure 12. New Registers with Asynchronous Reset Driven by rstb

Design Assistant detects that the two registers are reset synchronizers in this instance, causing another Design Assistant rule violation for rule-ID RES-50003 Asynchronous Reset Missing Timing Constraint.

Design Assistant reports that the reset signal feeding the asynchronous reset synchronizer is missing timing constraints:
Figure 13. RES-50003 Rule Violations

To resolve the violations in this example, perform the following steps:

  1. Check the rule Description and Recommendation.
    Figure 14. RES-50003 Rule Recommendation
  2. To implement the Recommendation, add the following constraint to the project SDC file:
    set_false_path -from [get_ports {rstb}]

The RES violations disappear after compiling the sample circuitry with the fixes.

Figure 15. RES Violations Resolved
Level Two Title