AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.1.1. Limit Reset Usage

Limit resets to design conditions that actually require reset. Limiting resets has the following benefits, especially for a large data path that can cause excessive resource usage:

  • Reduced logic utilization
  • Lower routing congestion
  • Lower data path routing delays
  • Better timing performance
However, you must assert a reset for any register that requires power-up to a known state. The following are some of the design scenarios that require resets:
  • If a watchdog timer detects a fault, then it can generate a reset to the whole system.
  • Status registers that require reset at certain events after taking action to clear any pending errors.
  • Simple counters or state machines that require return to initial states when conditions arise during a normal application run.
  • A flip-flop within a feedback loop requires a reset to bring the register back to a reset state during a normal process.

The following are some of the blocks or registers that can function without resets:

  • Shift registers and data buses accompanied by control signals to signify validity of current values.
  • Designs that use pipeline or delay chains may only require reset at the beginning of the pipeline stage, but not at the succeeding stages. Hold the reset asserted for a duration long enough to flush the entire pipeline.
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