AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

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ID 683539
Date 1/05/2021
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Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release Intel® FPGA IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

1.3.2. Example: Synchronous Reset Design Assistant Analysis

You can also use Design Assistant to identify and correct problematic synchronous reset conditions. In the following example, the reset synchronizer output incorrectly connects to a register reset using a different clock domain. Such a connection error can create functional design issues, especially if one domain is reset unnecessarily during normal operation.

Figure 16 shows an example where the reset synchronizer clocked on the clk1 domain connects to the u2_counter instance from the clk2 domain.

Figure 16. Reset Synchronizer used on Multiple Clock Domain
Design Assistant reports the following CDC rule violations in the Timing Analyzer folder of the Compilation Report for this condition:
Figure 17. Design Rule CDC-50001 Violations

Rule check CDC-50001 identifies two paths originating from FF2 of the reset synchronizer clocked by clk1, driving the u2_counter registers clocked by clk2. To resolve the violation for this example:

  1. Review the Design Assistant rule Description and Recommendation:
    Figure 18. Rule CDC-50001 Recommendation
  2. Implement a separate reset synchronizer for every clock domain, as the following figure shows:
    Figure 19. Separate Reset Synchronizer per Clock Domain
  3. Recompile the design changes. The synchronizer implementation corrects the CDC rule violations.
    Figure 20. CDC Rule Violations Corrected
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