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1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming
You can create a synchronous reset tree by duplicating the reset on every major design submodule that requires a reset on the same clock edge. You perform this duplication at the top level. You must add enough pipeline registers on every duplicate branch for use during retiming. You must ensure a balanced reset tree to have the same latency at all endpoints.
This manual process is the minimum duplication requirement to limit the fan-out of the synchronous reset. Thereafter, the Compiler attempts to retime the reset with the connected local logic. Depending on the logic size of every submodule driven by the duplicate branch, the Compiler may need to work harder to resolve all the reset path timing for every local duplicate branch.
You can add the preserve_syn_only attribute to the inserted pipeline registers to prevent the Compiler from optimizing out the registers during synthesis. For example:
Verilog HDL
(*preserve_syn_only*) reg dup_reg;VHDL
signal dup_reg : std_logic;
attribute preserve_syn_only : boolean;
attribute preserve_syn_only of dup_reg : signal is true;Figure 23 shows the circuit structure after inserting pipeline registers and duplicating this on every synchronous reset branch at the top level. After adding the registers, you compile the design to allow retiming of the registers as needed to resolve timing issues.
Important: To reset all the registers of a clock domain in the same clock cycle, the number of inserted pipeline registers must match in each branch.
Figure 23. Inserting Pipeline Registers on Synchronous Reset Tree
After the Retime stage, you can review the Retiming Limit Details Report to determine whether the number of pipeline registers is a limiting factor in meeting timing requirements, as the following example shows:
Figure 24. Retiming Limit Details in Fitter Retime Stage Folder
The Limiting Reason column specifies Insufficient Registers. The Critical Chain Details shows if the critical path is caused by the pipeline registers. You can add an additional pipeline register on all branches to keep them balanced and then recompile.
Figure 25. Retiming Limit Detail Report