AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

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ID 683531
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices A. Reference Design Files
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Stratix® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Stratix® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Intel® Stratix® 10 Partial Reconfiguration Controller IP Core 1.3.1.3.5. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
A. Reference Design Files

1.3.1. BSP Top

This Platform Designer system contains all the subsystems of this reference design. The system comprises of three main components - the top-level design, the PCIe* IP core, and the DDR4 External Memory Interfaces IP core. The system connects to external pins through the s10_pcie_ref_design.sv wrapper.


Section Content
PCI Express IP core
Intel Stratix 10 DDR4 External Memory Interfaces IP Core
Design Top

Level Two Title