AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

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ID 683531
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices A. Reference Design Files
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Stratix® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Stratix® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Intel® Stratix® 10 Partial Reconfiguration Controller IP Core 1.3.1.3.5. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
A. Reference Design Files

1.2.4. Bringing Up the Reference Design

The reference design is available in the following location:

https://github.com/intel/fpga-partial-reconfig

To access the reference design, navigate to the ref_designs sub-folder. Copy the s10_pcie_devkit_hpr folder to the home directory in your Linux system.

Before you begin: You must at least compile the base revision of the design.

To bring up the reference design on the board:
  1. Plug-in the Intel® Stratix® 10 GX FPGA development board to an available PCIe* slot in your host machine.
  2. Connect the host machine's ATX auxiliary power connector to the 12 V ATX input J4 of the development board.
  3. Power-up the host machine.
  4. Verify the micro-USB cable connection to the FPGA development board. Ensure that no other applications that use the JTAG chain are running.
  5. Navigate to the s10_pcie_devkit_hpr/software/installation folder in your system.
  6. This reference design uses a lower frequency memory reference clock than the default configuration on the device. To configure the memory reference clock to the correct frequency:
    1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
    2. Use the max5_116.pof file in the s10_pcie_devkit_hpr/software/installation directory to flash the MAX® V device on the Intel® Stratix® 10 GX FPGA Development Kit.
  7. Ensure that the DIP switch 1 is configured with both jumpers in the UP position.
    Important: Perform the above step only if you are bringing up the design for the first time. Otherwise, you can skip this step.
  8. To overwrite the existing factory image on the board with the reference design, execute the flash.pl script.
  9. Pass the JTAG cable number of your connected device as an argument to the script. (for example, perl flash.pl 1)
    Running this script configures the device with the contents of the flash.pof file. This parallel object file comes directly from the s10_pcie_devkit_hpr.sof file present in the output_files directory. The flash.pof file acts as the base image for the reference design.
    Note: Ensure successful compilation of the design before running this script.
  10. Turn-off the machine, reset DIP switch 1 to move the jumpers to the default position (UP, DOWN), and then turn-on the machine.
    Important: Perform the above step only if you are bringing up the design for the first time. Otherwise, you can simply power-cycle the host machine.
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