AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

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ID 683531
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices A. Reference Design Files
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Stratix® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Stratix® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Intel® Stratix® 10 Partial Reconfiguration Controller IP Core 1.3.1.3.5. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
A. Reference Design Files

A. Reference Design Files

Table 10.  Reference Design Files List
Type File/Folder Description
IP files

Contains the IP files for the Intel® Stratix® 10 External Memory Interfaces IP core, Intel® Stratix® 10 Hard IP for PCI Express* IP core, and devkit pins.

Contains the IP file for the Intel® Stratix® 10 Partial Reconfiguration Controller IP core, system description ROM, calibration I/O, and all the interface components.

Contains the freeze bridges, the region controller, and the JTAG SLD agent.

Contains all the IP files for the register file system, that is common across all personas.

Contains the JTAG SLD host for the PR region signal tapping. These files are applicable to all the personas.

Contains the JTAG SLD agent for the PR region signal tapping. These files are applicable to all the personas.

Contains all the IP files for EMIF interface in the PR personas.

Platform Designer System Files
Contains the following three Platform Designer (Standard) subsystems:
  • bsp_top.qsys—top-level subsystem, containing the PCIe* IP core and the External Memory Interfaces IP core.
  • design_top.qsys—static region, encompassing all the Avalon-MM interface logic, reset logic, and PR Region Controller IP core.
  • pr_subsystem.qsys—contains all the logic to communicate and interact with the PR region.

Contains the PR persona EMIF interface.
SystemVerilog design files

Contains the top-level wrapper. Also contains the SystemVerilog description for generic components in the three subsystems, and the PR region wrapper.

Contains all the source files for the basic DSP persona.

Contains all the source files for the basic arithmetic persona.

Contains all the source files for the Game of Life persona.

Contains all the source files for the DDR4 access persona.

Example personas that use the template for persona configuration. These examples demonstrate integrating a custom persona RTL into the reference design.

Memory files

Used for system description ROM.
Synopsys Design Constraints Files

Synthesis constraints for the design.

Provides exceptions.

JTAG timing constraints file.
Signal Tap File

Signal Tap file for the basic DSP persona.

Software utilities

Contains software utilites for flashing the development board, and communicating with the reference design.

Intel® Quartus® Prime Project File

Contains all the revisions.
Intel® Quartus® Prime Settings Files

Base revision settings file for the DDR4 access persona.

Implementation revision settings file for the DDR4 access persona.

Implementation revision settings file for basic DSP persona.

Implementation revision settings file for basic arithmetic persona.

Implementation revision settings file for Game of Life persona.

Implementation revision settings file for non-HPR parent DDR4 access persona.

Implementation revision settings file for non-HPR child basic arithmetic persona.

Implementation revision settings file for non-HPR child basic DSP persona.

Implementation revision settings file for non-HPR child GOL persona.

Template implementation revision settings file.

Verification

Contains testbench files for the design.

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