AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

Download PDF
ID 683531
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices A. Reference Design Files
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Stratix® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Stratix® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Intel® Stratix® 10 Partial Reconfiguration Controller IP Core 1.3.1.3.5. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
A. Reference Design Files

1.3.1.1. PCI Express* IP core

The Intel® Stratix® 10 Hard IP for PCI Express* IP core is a Gen2x8, with a 256-bit interface and running at 125 MHz.

The following table provides information on the configuration fields of the PCI Express* IP core that the reference design uses that are different from the default settings:
Table 3.   PCI Express* IP Core Configuration
Setting Parameter Value
System Settings Application interface type Avalon-MM with DMA
Hard IP mode Gen2:x8, Interface: 256-bit, 125 MHz
Port type Native endpoint
Avalon-MM Settings Enable control register access (CRA) Avalon-MM slave port Disable
Base Address Registers - BAR2 Type 32-bit non-prefetchable memory
Base Address Registers - BAR4 Type 32-bit non-prefetchable memory
Device Identification Registers Vendor ID 0x00001172
Device ID 0x00005052
Revision ID 0x00000001
Class code 0x00ea0001
Subsystem Vendor ID 0x00001172
Subsystem Device ID 0x00000001
PCI Express/PCI Capabilities - Device Maximum payload size 256 Bytes
PHY Characteristics Requested equalization far-end TX preset Preset 9
Note: Instantiate the PCI Express* IP core as part of a Platform Designer system.
Level Two Title