AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Public
Document Table of Contents

1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core

The ddr4_emif logic includes the Intel® Stratix® 10 External Memory Interfaces IP core. This IP core interfaces to the DDR4 external memory, with a 64-bit interface that runs at 933 MHz. Also, the IP core provides 2 GB of DDR4 SDRAM memory space. The EMIF Avalon-MM slave runs at 233 MHz clock.

The following table lists the configuration fields of the Intel® Stratix® 10 External Memory Interfaces IP core that are different from the Intel® Stratix® 10 GX FPGA Development Kit with DDR4 HILO preset settings:

Table 4.   Intel® Stratix® 10 DDR4 External Memory Interfaces IP Configuration
Setting Parameter Value
Memory - Topology DQ width

8

DQ pins per DQS group 8
Number of DQS groups 2
Alert# pin placement I/O Lane with DQS Group
DQS Group of ALERT# 0