Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

2.1.5. Design Example BAR Mappings

The following table shows the BAR mappings for different user modes and configurations:

Table 7.  BAR Mappings
User Mode Interface Design Example BAR Selected in MCDMA IP BAR Selected for PIO/BAM Design Example BAR Selected for BAS Design Example
MCDMA AVMM AVMM DMA BAR0 BAR2 N/A
PIO using Bypass mode BAR0 BAR2 N/A
AVST Device-side Packet Loopback BAR0 BAR2 N/A
Packet Generate/Check BAR0 BAR2 N/A
PIO using Bypass mode BAR0 BAR2 N/A
BAM + MCDMA AVMM AVMM DMA BAR0 BAR2 N/A
PIO using Bypass mode BAR0 BAR2 N/A
AVST Device-side Packet Loopback BAR0 BAR2 N/A
Packet Generate/Check BAR0 BAR2 N/A
PIO using Bypass mode BAR0 BAR2 N/A
BAM + BAS + MCDMA AVMM AVMM DMA BAR0 BAR2 BAR4
PIO using Bypass mode BAR0 BAR2 BAR4
AVST Device-side Packet Loopback BAR0 BAR2 BAR4
Packet Generate/Check BAR0 BAR2 BAR4
PIO using Bypass mode BAR0 BAR2 BAR4
BAM N/A PIO using Bypass mode N/A BAR0 and BAR2 N/A
BAM + BAS N/A Traffic Generator/Checker N/A BAR2 BAR0
PIO using Bypass mode N/A BAR2 BAR0
Data Mover Mode N/A PIO using Bypass mode N/A BAR2 N/A
External Descriptor Controller N/A BAR0 N/A