Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/17/2023
Public

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3.3.2. Supported Simulators

The following tables show supported simulators for MCDMA example designs.
Note: Root Port mode MCDMA IP simulation is supported by VCS simulator only.
Note: For 2x8 Hard IP modes, simulation is supported on PCIe0 only.
Note: MCDMA R-Tile PIO using Bypass design example simulation is supported. The remaining R-Tile design example simulations are not supported. This feature may be supported in a future release of the Intel® Quartus® Prime software.
Table 34.  Supported Simulators for MCDMA IP H-Tile
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition
H-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
Traffic Generator/Checker

BAM+BAS

Yes Yes Yes Yes No
Note: SR-IOV simulation support is provided only for 1 physical function and its VFs.
Note: SR-IOV is not supported for simulation in BAM+BAS+MCDMA mode.
Table 35.  Supported Simulators for MCDMA IP P-Tile
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition Aldec Riviera Pro
P-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

Data Mover Only

BAM+BAS+MCDMA

Yes Yes No Yes No No
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes No No No No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes No No No No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes No No No No
Traffic Generator/Checker BAM+BAS Yes Yes No No No No
External Descriptor Controller Data Mover Only Yes Yes No No No No
Note: SR-IOV is not supported in simulation
Table 36.  Supported Simulators for MCDMA IP F-Tile
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition
F-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

Data Mover Only

BAM+BAS+MCDMA

Yes Yes Yes Yes Yes
AVMM DMA

Multi channel DMA

BAM+MCDMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

BAM+BAS+MCDMA

Yes Yes Yes Yes No
Traffic Generator/Checker BAM_BAS Yes Yes Yes Yes No
External Descriptor Controller Data Mover Only Yes Yes No No No
Note: SR-IOV is not supported in simulation
Table 37.  Supported Simulators for MCDMA IP R-Tile
Tile Design Example User Mode VCS VCS MX Xcelium QuestaSim* Questa* Intel® FPGA Edition
R-Tile PIO using Bypass mode

Multi channel DMA

Bursting Master

BAM+BAS

BAM+MCDMA

Data Mover Only

Yes Yes No No No
AVMM DMA

Multi channel DMA

BAM+MCDMA

No No No No No
Device-side Packet Loopback

BAM + MCDMA

Multi channel DMA

No No No No No
Packet Generate/Check

BAM + MCDMA

Multi channel DMA

No No No No No
Traffic Generator/Checker BAM+BAS No No No No No
External Descriptor Controller Data Mover Only No No No No No
Note: SR-IOV is not supported in simulation