Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/17/2023
Public

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2.6.2. Hardware Test Results

The Custom Driver was used to generate the following output:
Figure 12. PIO Test-o option
Figure 13. H2D Avalon-MM Write-t option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 14. H2D Avalon-MM Write Intel Agilex® 7 F-Series P-Tile PCIe Gen4 x16 The following hardware test was run with Intel Agilex® 7 F-Series P-Tile PCIe Gen4 x16 configuration using Custom Driver.
Figure 15. H2D Avalon-MM Write with Data Validation Enabled-t -v option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Note: Hardware test with P-Tile Gen4 x16 may be added in a future release.
Figure 16. D2H Avalon-MM Read-r option. Note: This hardware test was run with the Intel® Stratix® 10 GX H-tile PCIe Gen3 x16 configuration.
Figure 17. D2H Avalon-MM Read Intel Agilex® 7 F-Series P-Tile PCIe Gen4 x16