Multi Channel DMA Intel® FPGA IP for PCI Express Design Example User Guide

ID 683517
Date 4/17/2023
Public

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3.5.2.4.4.3. BAM Test

  1. If the BAM support is enabled on hardware, enable the following flags in: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h
    __cflags += -UIFC_PIO_256 > 256b read/write operations on PIO BAR 
    	__cflags += -UIFC_PIO_128 > 128b read/write operations on PIO BAR
  2. Enable the below flag for 256b read or write operations in: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h
    __cflags += -DIFC_PIO_256

    Command: ./build/mcdma-test -- -b 0000:01:00.0 -o

  3. Enable the below flag for 128b read or write operations in: dpdk/dpdk/drivers/net/mcdma/rte_pmd_mcdma.h
    __cflags += -DIFC_PIO_128 
    __cflags += -UIFC_PIO_256
    Command: ./build/mcdma-test -- -b 0000:01:00.0 -o
    Figure 38. PIO 128b Write and Read Test
    Note: For BAM_BAS bitstream, undefine IFC_QDMA_INTF_AVST
    #undef IFC_QDMA_INTF_AVST in dpdk/ dpdk/drivers/net/mcdma/rte_pmd_mcdma.h