Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide

ID 683505
Date 8/05/2024
Public

1.5. Simulating the Design Example Testbench

Figure 7. Procedure

Follow these steps to simulate the testbench:

  1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."
    Table 3.  Steps to Simulate the Testbench
    Simulator Instructions
    Mentor Graphics ModelSim* SE* or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type
    vsim -c -do run_vsim.do
    Cadence NCSim In the command line, type sh run_ncsim.sh
    Cadence Xcelium* In the command line, type sh run_xcelium.sh
    Synopsys VCS* / VCS* MX In the command line, type sh run_vcs.sh or sh run_vcsmx.sh
    Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If RS-FEC is enabled or you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.

The successful test run displays output confirming the following behavior:

  1. Waiting for the ATX PLLs to lock.
  2. Waiting for RX transceiver reset to complete.
  3. Waiting for RX alignment.
  4. Sending ten packets.
  5. Receiving ten packets.
  6. Displaying Testbench complete.

The following sample output illustrates a successful simulation test run:

ATX PLLs Locked
***************************************************
***************  Transmit Ready   *****************
***************************************************
Waiting for the receiver to be ready
Receive transceivers are out of reset
Waiting for RX alignment
Rx Alignment Status Update 1/4: Word/Block lock is acquired over all virtual lanes
Rx Alignment Status Update 2/4: Virtual lanes Ordered
Rx Alignment Status Update 3/4: RX deskew lock acquired
Rx Alignment Status Update 4/4: RX alignment lock acquired
Rx is fully aligned with Tx
***************************************************
**************   Receive Ready   ******************
***************************************************
Transmitting test data
** Sending Packet           1...
** Sending Packet           2...
** Sending Packet           3...
** Sending Packet           4...
** Sending Packet           5...
** Sending Packet           6...
** Sending Packet           7...
** Sending Packet           8...
** Sending Packet           9...
** Sending Packet          10...
** Received Packet          1...
** Received Packet          2...
** Received Packet          3...
** Received Packet          4...
** Received Packet          5...
** Received Packet          6...
** Received Packet          7...
** Received Packet          8...
** Received Packet          9...
** Received Packet         10...
**
** Testbench complete.
**
*****************************************