Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling the Compilation-Only Project 1.7. Compiling and Configuring the Design Example in Hardware 1.8. Testing the Hardware Design Example
1.8. Testing the Hardware Design Example x
1.8.1. Testing the Hardware Design Example using Ethernet Link Inspector 1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide

1.7. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/alt_e100s10.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in your <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Stratix® 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Stratix® 10 Transceiver Signal Integrity Development Kit to which your Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.
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