Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling the Compilation-Only Project 1.7. Compiling and Configuring the Design Example in Hardware 1.8. Testing the Hardware Design Example
1.8. Testing the Hardware Design Example x
1.8.1. Testing the Hardware Design Example using Ethernet Link Inspector 1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide

5. Document Revision History for the Low Latency 100G Ethernet Stratix® 10 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP version Changes
2024.08.05 24.2 22.2.0
  • Updated instructions for ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition simulators in Low Latency 100G Ethernet Stratix® 10 FPGA Core Testbench File Descriptions table.
  • Updated description for run_vsim.do filename in Steps to Simulate the Testbench table.
2021.01.27 20.3 — Added new topic: Ethernet Toolkit
2020.04.13 20.1 19.2.0
  • Updated the Low Latency 100G Ethernet Intel Stratix 10 FPGA Simulation Design Example Block Diagram and the Low Latency 100G Ethernet Intel Stratix 10 FPGA Hardware Design Example High Level Block Diagram to emphasize that the 2nd ATX PLL configures as a clock buffer.
  • Corrected the register type in the Design Example Registers section. The 0x000300 word offset represents PHY registers, not RX PHY registers.
  • Added PMA registers word offset in the Design Example Registers section.
2019.12.16 19.4 19.1.1
  • Added note to clarify run_vcs.sh and run_vcsmx.sh usage.
  • Updated sample output in the Testing the Hardware Design Example section.
  • Added a new topic: Testing the Hardware Design Example using System Debugging Toolkits
2019.09.30 19.3 19.1.1
  • Added Synopsys VCS script option run_vcsmx.sh in Low Latency 100G Ethernet Stratix® 10 FPGA Core Testbench File Descriptions and Steps to Simulate the Testbench tables.
  • Added support for Xcelium* simulator.
  • Updated Generating the Design section.
  • Updated .sof file path in the Compiling and Configuring the Design Example in Hardware section.
  • Added Ethernet Link Inspector in the Testing the Hardware Design Example section.
  • Updated Packet Number Control and PKT_GEN_TX_CTRL registers in the Packet Client Registers table.
  • Added Packet Generator Programming Sequence section.
2019.05.15 19.1 19.1 Changed word "lower" to "upper" in the Source address register.
2018.06.29 18.0 18.0
  • Added flow control feature in the DUT features list.
  • Added 322.2625 MHz support for PHY reference clock.
  • Added packet client registers description in the Packet Client Registers table.
2017.11.06 17.1 17.1 Initial release.
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