1.3. Hardware Design Example Components
Figure 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA Hardware Design Example High Level Block Diagram
The Low Latency 100G Ethernet Intel Stratix 10 FPGA hardware design example includes the following components:
- Low Latency 100G Ethernet Intel Stratix 10 FPGA core.
- Client logic that coordinates the programming of the IP core and packet generation.
- One ATX PLL and one clock buffer to drive the device transceiver channels.
- IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
- JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
The hardware design example uses run_test command to initiate packet transmission from packet generator to the IP core. Use the loop_on command to turn on internal serial loopback for this design example. If the internal serial loopback is turned on, the IP core receives the packets and transmit to the packet generator. The MAC checks the received packets and updates the statistic counters. Use the chkmac_stats command in the system console to read and print out the MAC statistic registers once the packet transmissions completed.
| File Names |
Description |
|---|---|
| alt_e100s10.qpf | Quartus® Prime project file |
| alt_e100s10.qsf | Quartus® Prime project settings file |
| alt_e100s10.sdc, alt_e100s10_clock.sdc | Synopsys Design Constraints files. You can copy and modify these files for your own Low Latency 100G Ethernet Intel Stratix 10 FPGA design. |
| alt_e100s10.v | Top-level Verilog HDL design example file |
| common/ | Hardware design example support files |
| hwtest/main.tcl | Main file for accessing System Console |