Visible to Intel only — GUID: ayj1585668992814
Ixiasoft
Visible to Intel only — GUID: ayj1585668992814
Ixiasoft
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
Updated for: |
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Intel® Quartus® Prime Design Suite 24.2 |
IP Version 22.2.0 |
The Low Latency E-Tile 40G Ethernet (LL E-Tile 40GbE) Intel® FPGA IP is used in multiple variants of the Stratix® 10 and Agilex™ 7device families. The IP core implements the IEEE 802.3-2010 40G Ethernet Standard and includes options to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
The MAC client side interface for the Low Latency E-Tile 40G Ethernet Intel® FPGA IP is a 128-bit Avalon® streaming interface and a 32-bit Avalon® memory-mapped interface control path. The network interfaces are standard XLAUI interfaces.
The IP provides standard media access control (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) functions.