Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes

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ID 683289
Date 7/12/2024
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1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes
1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes x
1.1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v22.2.0 1.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v21.0.0 1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v20.0.0 1.4. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v19.1.0 1.5. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives 1.6. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide Archives
1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes

1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:

  • X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Section Content
Low Latency E-Tile 40G Ethernet Intel FPGA IP v22.2.0
Low Latency E-Tile 40G Ethernet Intel FPGA IP v21.0.0
Low Latency E-Tile 40G Ethernet Intel FPGA IP v20.0.0
Low Latency E-Tile 40G Ethernet Intel FPGA IP v19.1.0
Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide Archives
Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example User Guide Archives

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