Visible to Intel only — GUID: esb1471031194997
Ixiasoft
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
Visible to Intel only — GUID: esb1471031194997
Ixiasoft
3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options
The Low Latency E-Tile 40G Ethernet parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus® Prime Pro Edition software.
- In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
- Click OK. The parameter editor appears.
- On the IP tab, specify the parameters for your IP core variation. Refer to Low Latency E-Tile 40G Ethernet IP Core Parameters for information about specific IP core parameters.
- Optionally, to generate a simulation testbench or compilation and hardware design example, follow the instructions in the Low Latency E-Tile 40G Ethernet Design Example User Guide .
- Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
- Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Related Information