Visible to Intel only — GUID: zxs1585686456549
Ixiasoft
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
Visible to Intel only — GUID: zxs1585686456549
Ixiasoft
3.5.2. Ethernet Adaptation Flow
Refer to Loading a PMA Configuration and PMA Registers 0x200 to 0x203 Usage sections in the E-tile Transceiver PHY User Guide for more details on the adaptation flow and how to get started.
This adaptation flow assumes a valid Ethernet traffic.
- Assert tx_rst_n and rx_rst_n signals.
- Trigger PMA analog.
- Reload PMA settings and call PMA attribute sequencer on all lanes.
- Apply control status registers (CSR) reset.
- Deassert the tx_rst_n signal.
- If using a PMA configuration, load the PMA configuration using control status registers (CSR). This is loaded to the registers using PMA registers 0x200 to 0x203 1.
- Write 0x40143 = 0x80.
- Read 0x40144[0] until it changes to 1.
- Enable internal serial loopback 2 and run initial adaptation. Verify that the initial adaptation status is complete using interrupt code 0x0126 and data 0x0B00.
- Enable mission mode and disable internal serial loopback (skip this step if using internal serial loopback)2.
- Wait for valid data traffic on RX and then proceed to the next step.
- Run initial adaptation. Verify that the initial adaptation status is complete using interrupt code 0x0126 and data 0x0B00 (skip this step if using internal serial loopback).
- Run continuous adaptation 3.
- Deassert the rx_rst_n signal.
- Optional: Verify that the link status signal rx_aligned transitions high.
- Send packets.
1 Refer to Loading a PMA Configuration and PMA Registers 0x200 to 0x203 Usage.
2 For how to enable and disable internal serial loopback, refer to 0x0008: Internal Serial Loopback and Reverse Parallel Loopback Control.
3 During the continuous adaptation, the link partner must keep sending the data. If link goes down, the entire sequence must be repeated.