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1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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4.1.2.2. IP Core Strict SFD Checking
The Low Latency E-Tile 40G Ethernet core RX MAC checks all incoming packets for a correct Start byte (0xFB). If you turn on Enable Strict SFD check in the Low Latency E-Tile 40G Ethernet parameter editor, you enable the RX MAC to check the incoming preamble and SFD for the following values:
- SFD = 0xD5
- Preamble = 0x555555555555
The RX MAC checks one or both of these values depending on the values in bits [4:3] of the RXMAC_CONTROL register at offset 0x50A.
Enable Strict SFD check | 0x50A[4]: Preamble Check | 0x50A[3]: SFD Check | Fields Checked | Behavior if Check Fails |
---|---|---|---|---|
Off | Don't Care | Don't Care | Start byte | IP core does not recognize a malformed Start byte as a Start byte |
On | 0 | 0 | Start byte | |
0 | 1 | Start byte and SFD | IP Core drops the packet | |
1 | 0 | Start byte and preamble | ||
1 | 1 | Start byte and preamble and SFD |