Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 7/12/2024
Public
Document Table of Contents

1.4. Resource Utilization

Resource utilization changes depending on the parameter settings you specify in the Low Latency E-Tile 40G Ethernet parameter editor. For example, if you turn on statistics counters in the Low Latency E-Tile 40G Ethernet parameter editor, the IP core requires additional resources to implement the additional functionality.

Table 5.  IP Core Variation Encoding for Resource Utilization Table"On" indicates the parameter is turned on. The symbol "—" indicates the parameter is turned off or not available.
IP Core Variation A B C E F
Parameter
Ready latency 0 0 3 3 3
Enable TX CRC insertion On On On On
Enable link fault generation On
Enable preamble passthrough On
Enable MAC stats counters On On On On
Enable Strict SFD check On On
Table 6.  IP Core FPGA Resource Utilization in Stratix® 10 deviceLists the resources and expected performance for selected variations of the Low Latency E-Tile 40G Ethernet IP core in a Stratix® 10 device.

These results were obtained using the Quartus® Prime 20.1 software version.

  • The numbers of ALMs and logic registers are rounded up to the nearest 100.
  • The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus® Prime Fitter Report.

IP Core Variation

ALMs

Dedicated Logic Registers

Memory

M20K

A 7,584 18,644 1
B 11,480 27,379 1
C 12,086.5 28,676 1
E 11,455.3 26,941 1
F 11,712 28,104 1
Table 7.  IP Core FPGA Resource Utilization in Agilex™ 7 deviceLists the resources and expected performance for selected variations of the Low Latency E-Tile 40G Ethernet IP core in a Agilex™ 7 device.

These results were obtained using the Quartus® Prime 20.2 software version.

IP Core Variation

ALMs

Dedicated Logic Registers

Memory

M20K

A 7,379.9 15,958 1
B 11,207 24,538 1
C 11,912.4 26,210 1
E 11,393.9 25,237 1
F 11,468.7 25,454 1