AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

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ID 683478
Date 12/18/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9144 Configurations 1.5. Test Results 1.6. Test Results Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

1.3.2. Transmitter Transport Layer

To verify the data integrity of the payload data stream through the TX JESD204B IP core and transport layer, the DAC's JESD core is configured to check either the PRBS test pattern that the FPGA's test pattern generator transmits. The DAC JESD core checks the transport layer test patterns based on F = 1, 2, 4, or 8 configuration. You can check the DAC registers 0x14C and 0x14D for individual DAC’s error status.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog domain, the FPGA is configured to generate a sinewave. Connect an oscilloscope to observe the waveform at the DAC analog channels.

Figure 3. Data Integrity Check Block DiagramThis figure shows the conceptual test setup for data integrity checking.

The SignalTap II Logic Analyzer tool monitors the operation of the TX transport layer.

Table 3.  Transport Layer Test Cases

Test Case

Objective

Description

Passing Criteria

TL.1

Check the transport layer mapping using PRBS-7 test pattern.

The following signals in altera_jesd204_transport_tx_top.sv are tapped:

  • jesd204_tx_data_valid
  • jesd204_tx_data_ready

The following signal in jesd204b_ed.sv is tapped:

  • jesd204_tx_int

The txframe_clk is used as the sampling clock for the SignalTap II.

Check the following error in the AD9144 register:

  • PRBS Error
  • The jesd204_tx_data_valid and jesd204_tx_data_ready signals are asserted.
  • The PRBS Error bit in the AD9144 registers 0x14C and 0x14D are deasserted. The jesd204_tx_int signal is also deasserted.
TL.2 Verify the data transfer from digital to analog domain. Enable sinewave generator in the FPGA and observe the DAC analog channel output on the oscilloscope. A monotone sinewave is observed on the oscilloscope.
Level Two Title