1.3.4. Deterministic Latency (Subclass 1)
Figure below shows a block diagram of the deterministic latency test setup. The AD9516-1 clock generator on the AD9144 EVM provides periodic SYSREF pulses for both the DAC and JESD204B IP core. The period of SYSREF pulses is configured to two Local Multi Frame Clocks (LMFC). The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.
Figure 4. Deterministic Latency Test Setup Block Diagram
The FPGA generates a 16-bit digital sample with a value of 8000 hexadecimal number at the transport layer. The most significant bit of this digital sample has a logic 1 and this bit is an output pin at the FPGA. This bit is probed at channel 1 of the oscilloscope. The DAC analog channel is probed at channel 2 of the oscilloscope. With two's complement value of 8000h, a pulse with the amplitude of negative full range is expected at channel 1 of the DAC analog. The time difference between the pulses at channel 1 (t0) and channel 2 (t1) is measured. This is the total latency of the JESD204B link, the DAC digital blocks, and the analog channel.
| Test Case | Objective | Description | Passing Criteria |
|---|---|---|---|
| DL.1 | Measure the total latency. | Measure the time difference between the rising edge of pulses at oscilloscope channel 1 and 2. | The latency should be consistent. |
| DL.2 | Re-measure the total latency after DAC power cycle and FPGA reconfiguration. | Measure the time difference between the rising edge of pulses at oscilloscope channel 1 and 2. | The latency should be consistent. |