AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

Download PDF
ID 683478
Date 12/18/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9144 Configurations 1.5. Test Results 1.6. Test Results Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

1.3.1. Transmitter Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane alignment sequence.

On link start-up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool monitors the transmitter data link layer operation.


Section Content
Code Group Synchronization (CGS)
Initial Frame and Lane Synchronization

Level Two Title