AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

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ID 683478
Date 12/18/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9144 Configurations 1.5. Test Results 1.6. Test Results Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

1.4. JESD204B IP Core and AD9144 Configurations

The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9144 device's configuration registers. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9144 operating conditions.

The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.

Table 6.  Parameter Configuration

Configuration

Mode

Mode

Mode

Mode

Mode

Mode

Mode

Mode

Mode

Mode

LMF

841

842

442

244

421

422

222

124

211

112

HD

1

0

0

0

1

0

0

0

1

0

S

1

2

1

1

1

2

1

1

1

1

N

16

16

16

16

16

16

16

16

16

16

N’

16

16

16

16

16

16

16

16

16

16

CS

0

0

0

0

0

0

0

0

0

0

CF

0

0

0

0

0

0

0

0

0

0

DAC Sampling Clock (MHz)

983.04

983.04

491.52

245.76

983.04

983.04

491.52

245.76

983.04

491.52

FPGA Device Clock (MHz) 4

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

FPGA Management Clock (MHz)

100

100

100

100

100

100

100

100

100

100

FPGA Frame Clock (MHz)

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

FPGA Link Clock (MHz) 5

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

245.76

Character Replacement

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Data Pattern
  • PRBS-7
  • Sine 6
  • Single Pulse 7
4 The device clock is used to clock the transceiver.
5 The frame clock and link clock are derived from the device clock using an internal PLL.
6 The sinewave pattern is used in TL.2 and SCR.2 test cases to verify that the pattern generated in the FPGA transport layer is transmitted by the DAC analog channel.
7 The single pulse pattern is used in deterministic latency measurement test cases DL.1 and DL.2 only.
Level Two Title