AN 749: Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

Download PDF
ID 683478
Date 12/18/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and AD9144 Configurations 1.5. Test Results 1.6. Test Results Comments 1.7. Document Revision History
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9144 Hardware Checkout Report

1.2. Hardware Setup

Figure 1. Hardware SetupThe ADI AD9144 daughter card module connects to the Arria 10 GX development board’s FMC connector.
  • The AD9144 EVM derives power from the Arria 10 FMC port.
  • A reference clock, which is equal to the DAC sampling clock, is provided to the DAC through SMA pin J1. An internal clock source (AD9516-1) present on the DAC EVM uses this reference and provides the device clock to both the DAC and FPGA.
  • For subclass 1, the AD9516-1 clock generator generates SYSREF for the JESD204B IP core as well as the AD9144 device.
  • The sync_n signal is also transmitted from the AD9144 to FPGA through the FMC pins.
  • To configure the DAC using SPI over FMC, short the pads at JP3 by soldering it. The location of JP3 is beside XP1 header. In addition, the PIC controller must be held in reset by putting a jumper at pin 5 and 6 of the XP1 header.
Figure 2. System-Level Block DiagramThe system-level block diagram shows how different modules connect in this design.

In this setup, where the LMF=841, the data rate of transceiver lanes is 9.8304 Gbps. A clock source on the EVM (AD9516) provides 245.76 MHz clock to the FPGA and 983.04 MHz sampling clock to the AD9144. The AD9516 provides SYSREF pulses to both the AD9144 and FPGA. The AD9144 provides the sync_n signal through the FMC pins. The AD9144 operates in LINK0 only mode (single link) in all configurations.

Level Two Title