Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Managing Intel® Quartus® Prime Projects 4. Design Planning 5. Introduction to Intel® FPGA IP Cores 6. Migrating to Intel® Quartus® Prime Pro Edition 7. Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
2.1. FPGA Basic Design Prerequisites 2.2. Selecting an Intel® Quartus® Prime Software Edition 2.3. Introduction to Intel® Quartus® Prime Pro Edition Revision History
3. Managing Intel® Quartus® Prime Projects x
3.1. Creating a New FPGA Design Project 3.2. Viewing Basic Project Information 3.3. Intel® Quartus® Prime Project Contents 3.4. Managing Project Settings 3.5. Managing Logic Design Files 3.6. Managing Timing Constraints 3.7. Integrating Other EDA Tools 3.8. Exporting Compilation Results 3.9. Migrating Projects Across Operating Systems 3.10. Archiving Projects 3.11. Command-Line Interface 3.12. Managing Projects Revision History
3.1. Creating a New FPGA Design Project x
3.1.1. Using the Board-Aware Flow
3.1.1. Using the Board-Aware Flow x
3.1.1.1. Creating a New Project from a Design Example 3.1.1.2. Specifying a Target Board for the Project
3.1.1.1. Creating a New Project from a Design Example x
3.1.1.1.1. Family, Device & Board Settings 3.1.1.1.2. Accessing Pre-Installed Design Examples 3.1.1.1.3. Accessing Online Design Examples 3.1.1.1.4. Accessing Downloaded Design Examples
3.1.1.1.3. Accessing Online Design Examples x
3.1.1.1.3.1. Internet Connectivity Options 3.1.1.1.3.2. Design Examples Options
3.2. Viewing Basic Project Information x
3.2.1. Using the Compilation Dashboard 3.2.2. Viewing Project Reports 3.2.3. Viewing Project Messages
3.2.3. Viewing Project Messages x
3.2.3.1. Viewing Synthesis Warning Messages 3.2.3.2. Suppressing Message Display 3.2.3.3. Promoting Critical Warnings to Errors
3.3. Intel® Quartus® Prime Project Contents x
3.3.1. Project File Best Practices
3.4. Managing Project Settings x
3.4.1. Optimizing Project Settings
3.4.1. Optimizing Project Settings x
3.4.1.1. Optimize Settings with Design Space Explorer II 3.4.1.2. Optimize Settings with Project Revisions 3.4.1.3. Back-Annotate Optimized Assignments
3.5. Managing Logic Design Files x
3.5.1. Including Design Libraries 3.5.2. Creating a Project Copy
3.8. Exporting Compilation Results x
3.8.1. Exporting a Version-Compatible Compilation Database 3.8.2. Importing a Version-Compatible Compilation Database 3.8.3. Creating a Design Partition 3.8.4. Exporting a Design Partition 3.8.5. Reusing a Design Partition 3.8.6. Viewing Quartus Database File Information 3.8.7. Clearing Compilation Results
3.8.6. Viewing Quartus Database File Information x
3.8.6.1. QDB File Attribute Types
3.9. Migrating Projects Across Operating Systems x
3.9.1. Migrating Design Files and Libraries 3.9.2. Design Library Migration Guidelines
3.9.1. Migrating Design Files and Libraries x
3.9.1.1. Use Relative Paths
3.10. Archiving Projects x
3.10.1. Manually Adding Files To Archives 3.10.2. Archiving Projects for Service Requests 3.10.3. Archiving Projects for External Revision Control 3.10.4. Creating Database-Only Archives
3.10.3. Archiving Projects for External Revision Control x
3.10.3.1. Project Files to Include In External Revision Control
3.11. Command-Line Interface x
3.11.1. Project Revision Commands 3.11.2. Project Archive Commands 3.11.3. Project Database Commands
3.11.3. Project Database Commands x
3.11.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
4. Design Planning x
4.1. Design Planning 4.2. Create a Design Specification and Test Plan 4.3. Plan for the Target Device or Board 4.4. Plan for Intellectual Property Cores 4.5. Plan for Standard Interfaces 4.6. Plan for Device Programming 4.7. Plan for Device Power Consumption 4.8. Plan for Interface I/O Pins 4.9. Plan for other EDA Tools 4.10. Plan for On-Chip Debugging Tools 4.11. Plan HDL Coding Styles 4.12. Plan for Hierarchical and Team-Based Designs 4.13. Design Planning Revision History
4.3. Plan for the Target Device or Board x
4.3.1. Device Migration Planning
4.9. Plan for other EDA Tools x
4.9.1. Third-Party Synthesis Tools 4.9.2. Third-Party Simulation Tools
4.11. Plan HDL Coding Styles x
4.11.1. Design Recommendations 4.11.2. Recommended HDL Coding Styles 4.11.3. Managing Metastability
4.12. Plan for Hierarchical and Team-Based Designs x
4.12.1. Flat Compilation without Design Partitions
5. Introduction to Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.8. Scripting IP Core Generation 5.9. Modifying an IP Variation 5.10. Upgrading IP Cores 5.11. Simulating Intel® FPGA IP Cores 5.12. Generating Simulation Files for Platform Designer Systems and IP Variants 5.13. Synthesizing IP Cores in Other EDA Tools 5.14. Instantiating IP Cores in HDL 5.15. Support for the IEEE 1735 Encryption Standard 5.16. Introduction to Intel FPGA IP Cores Revision History
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. Applying Preset Parameters for Specific Applications 5.6.2. Customizing IP Presets
5.6.1. Applying Preset Parameters for Specific Applications x
5.6.1.1. Viewing, Applying, and Deleting IP Presets
5.6.2. Customizing IP Presets x
5.6.2.1. Defining Preset Pin Assignments
5.6.2.1. Defining Preset Pin Assignments x
5.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 5.6.2.1.2. Defining Preset Pin Assignments in a Pin File
5.10. Upgrading IP Cores x
5.10.1. Upgrading IP Cores at Command-Line 5.10.2. Migrating IP Cores to a Different Device 5.10.3. Troubleshooting IP or Platform Designer System Upgrade
5.11. Simulating Intel® FPGA IP Cores x
5.11.1. Generating IP Simulation Files 5.11.2. Scripting IP Simulation
5.11.2. Scripting IP Simulation x
5.11.2.1. Generating a Combined Simulator Setup Script
5.14. Instantiating IP Cores in HDL x
5.14.1. Example Top-Level Verilog HDL Module 5.14.2. Example Top-Level VHDL Module
6. Migrating to Intel® Quartus® Prime Pro Edition x
6.1. Keep Pro Edition Project Files Separate 6.2. Upgrade Project Assignments and Constraints 6.3. Upgrade IP Cores and Platform Designer Systems 6.4. Upgrade Non-Compliant Design RTL 6.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
6.2. Upgrade Project Assignments and Constraints x
6.2.1. Modify Entity Name Assignments 6.2.2. Resolve Timing Constraint Entity Names 6.2.3. Verify Generated Node Name Assignments 6.2.4. Replace Logic Lock (Standard) Regions 6.2.5. Modify Signal Tap Logic Analyzer Files 6.2.6. Remove References to .qip Files 6.2.7. Remove Unsupported Feature Assignments
6.2.4. Replace Logic Lock (Standard) Regions x
6.2.4.1. Logic Lock Region Assignment Examples
6.4. Upgrade Non-Compliant Design RTL x
6.4.1. Verify Verilog Compilation Unit 6.4.2. Update Entity Auto-Discovery 6.4.3. Ensure Distinct VHDL Namespace for Each Library 6.4.4. Remove Unsupported Parameter Passing 6.4.5. Remove Unsized Constant from WYSIWYG Instantiation 6.4.6. Remove Non-Standard Pragmas 6.4.7. Declare Objects Before Initial Values 6.4.8. Confine SystemVerilog Features to SystemVerilog Files 6.4.9. Avoid Assignment Mixing in Always Blocks 6.4.10. Avoid Unconnected, Non-Existent Ports 6.4.11. Avoid Illegal Parameter Ranges 6.4.12. Update Verilog HDL and VHDL Type Mapping
6.4.1. Verify Verilog Compilation Unit x
6.4.1.1. Verilog HDL Configuration Instantiation
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Managing Intel® Quartus® Prime Projects
4. Design Planning
5. Introduction to Intel® FPGA IP Cores
6. Migrating to Intel® Quartus® Prime Pro Edition
7. Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

3.12. Managing Projects Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.04.03 23.1
  • Updated product family name to "Intel Agilex 7."
2022.12.12 22.4
  • Revised Creating a New FPGA Design Project for board-aware features.
  • Added Using the Board-Aware Flow topic.
  • Added Creating a New Project from a Design Example topic.
  • Added Family, Device & Board Settings topic.
  • Added Accessing Pre-Installed Design Examples topic.
  • Added Accessing Online Design Examples topic.
  • Added Accessing Downloaded Design Examples topic.
  • Added Internet Connectivity Options topic.
  • Added Design Examples Options topic.
  • Added Specifying a Target Board for the Project topic.
2022.03.28 22.1
  • Removed references to obsolete Advisors from Optimizing Project Settings topic.
  • Added Viewing Synthesis Warning Messages topic.
  • Removed the topic Automated Problem Reports.
2021.06.21 21.2
  • Added Version-Compatible Compilation Database Support table.
  • Added "Promoting Critical Warnings to Errors" topic.
2021.03.29 21.1
  • Added "Creating Database-Only Archives" topic.
  • Added "Promoting Critical Warnings to Errors" topic
2020.09.28 20.3
  • Updated "Back-Annotate Optimized Assignments" for support of pins, clocks, RAMs, and DSPs.
2020.05.01 20.1
  • Added note about .qar file requirements to "Design Guidelines for Component Instances" topic.
2019.09.30 19.3
  • Added "Disabling Automated Problem Reports" topic.
  • Added "Suppressing Messages" topic.
2018.09.24 18.1
  • Subdivided "Exporting, Archiving, and Migrating Projects" into separate sections.
  • Described migration of full chip database in "Exporting a Version-Compatible Compilation Database" topic.
  • Described automated .qdb partition export in "Exporting a Design Partition" topic.
  • Added "Viewing Quartus Database File Information" topic.
  • Added "Specifying the Target Device or Board" topic.
  • Divided "Introduction to Intel FPGA IP Cores" into separate chapter.
  • Moved "IP Core Best Practices" topic to Introduction to Intel FPGA IP Cores chapter.
  • Moved "Factors Affecting Compilation Results" topic to Design Compilation: Intel Quartus Prime Pro Edition User Guide.
2018.05.07 18.0.0
  • Initial release as chapter of Getting Started User Guide.
  • Revised "Exporting a Design Partition" topic to add Include entity-bound SDC files for the selected partition option, to add prerequisite steps, and to remove import step covered in separate topic.
  • Changed title of "Managing Team-Based Designs" to "Exporting, Archiving, and Migrating Projects" and updated content.
  • Changed title of "Migrating Compilation Results Across Software Versions" to "Exporting the Compilation Database" and updated content.
  • Changed title of "Exporting the Results Database" to "Exporting a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Importing the Results Database" to "Importing a Version-Compatible Design Compilation Database" and updated content.
  • Changed title of "Cleaning the Project Database" to "Cleaning the Project Compilation Database."
  • Updated screenshots of IP Catalog and Parameter Editor for latest IP names.
Date Version Changes
2017.11.06 17.1.0
  • Revised product branding for Intel® standards.
  • Revised topics on Intel® FPGA IP Evaluation Mode (formerly OpenCore).
  • Removed -compatible attribute from export_design command content.
  • Updated figure: IP Upgrade Alert in Project Navigator.
  • Updated IP Core Upgrade Status table with new icons, and added row for IP Component Outdated status.
2017.05.08 17.0.0
  • Added Project Tasks pane and update New Project Wizard.
  • Updated Compilation Dashboard image to show concurrent analysis.
  • Removed Smart Compilation option from Settings dialog box screenshot.
  • Updated IP Catalog screenshots for latest GUIs.
  • Added topic on Back-Annotate Assignments command.
  • Added Exporting a Design Partition topic.
  • Removed mentions to deprecated Incremental Compilation.
  • Added reference to Block-Level Design Flows.
2016.10.31 16.1.0
  • Added references to compilation stages and snapshots.
  • Removed support for comparing revisions.
  • Added references to .ip file creation during Intel® Quartus® Prime Pro Edition stand-alone IP generation.
  • Updated IP Core Generation Output files list and diagram.
  • Added Support for IP Core Encryption topic.
  • Rebranding for Intel
2016.05.03 16.0.0
  • Removed statements about serial equivalence when using multiple processors.
  • Added the "Preserving Compilation Results" section.
  • Added the "Migrating Results Across Quartus Prime Software" section and its subsections for information about importing and exporting compilation results between different versions of Quartus Prime.
  • Added the "Project Database Commands" section and its subsections.
2016.02.09 15.1.1
  • Clarified instructions for Generating a Combined Simulator Setup Script.
  • Clarified location of Save project output files in specified directory option.
2015.11.02 15.1.0
  • Added Generating Version-Independent IP Simulation Scripts topic.
  • Added example IP simulation script templates for supported simulators.
  • Added Incorporating IP Simulation Scripts in Top-Level Scripts topic.
  • Added Troubleshooting IP Upgrade topic.
  • Updated IP Catalog and parameter editor descriptions for GUI changes.
  • Updated IP upgrade and migration steps for latest GUI changes.
  • Updated Generating IP Cores process for GUI changes.
  • Updated Files Generated for IP Cores and Qsys system description.
  • Removed references to devices and features not supported in version 15.1.
  • Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0
  • Added description of design templates feature.
  • Updated screenshot for DSE II GUI.
  • Added qsys_script IP core instantiation information.
  • Described changes to generating and processing of instance and entity names.
  • Added description of upgrading IP cores at the command line.
  • Updated procedures for upgrading and migrating IP cores.
  • Gate level timing simulation supported only for Cyclone IV and Stratix IV devices.
2014.12.15 14.1.0
  • Updated content for DSE II GUI and optimizations.
  • Added information about new Assignments > Settings > IP Settings that control frequency of synthesis file regeneration and automatic addition of IP files to the project.
2014.08.18

14.0a10.0

  • Added information about specifying parameters for IP cores targeting Arria 10 devices.
  • Added information about the latest IP output for version 14.0a10 targeting Arria 10 devices.
  • Added information about individual migration of IP cores to the latest devices.
  • Added information about editing existing IP variations.
2014.06.30 14.0.0
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
November 2013 13.1.0
  • Conversion to DITA format
May 2013 13.0.0
  • Overhaul for improved usability and updated information.
June 2012 12.0.0
  • Removed survey link.
  • Updated information about VERILOG_INCLUDE_FILE.
November 2011 10.1.1 Template update.
December 2010 10.1.0
  • Changed to new document template.
  • Removed Figure 4–1, Figure 4–6, Table 4–2.
  • Moved “Hiding Messages” to Help.
  • Removed references about the set_user_option command.
  • Removed Classic Timing Analyzer references.
Level Two Title