Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Introduction to Intel® Quartus® Prime Pro Edition 3. Managing Intel® Quartus® Prime Projects 4. Design Planning 5. Introduction to Intel® FPGA IP Cores 6. Migrating to Intel® Quartus® Prime Pro Edition 7. Document Archives A. Intel® Quartus® Prime Pro Edition User Guides
2. Introduction to Intel® Quartus® Prime Pro Edition x
2.1. FPGA Basic Design Prerequisites 2.2. Selecting an Intel® Quartus® Prime Software Edition 2.3. Introduction to Intel® Quartus® Prime Pro Edition Revision History
3. Managing Intel® Quartus® Prime Projects x
3.1. Creating a New FPGA Design Project 3.2. Viewing Basic Project Information 3.3. Intel® Quartus® Prime Project Contents 3.4. Managing Project Settings 3.5. Managing Logic Design Files 3.6. Managing Timing Constraints 3.7. Integrating Other EDA Tools 3.8. Exporting Compilation Results 3.9. Migrating Projects Across Operating Systems 3.10. Archiving Projects 3.11. Command-Line Interface 3.12. Managing Projects Revision History
3.1. Creating a New FPGA Design Project x
3.1.1. Using the Board-Aware Flow
3.1.1. Using the Board-Aware Flow x
3.1.1.1. Creating a New Project from a Design Example 3.1.1.2. Specifying a Target Board for the Project
3.1.1.1. Creating a New Project from a Design Example x
3.1.1.1.1. Family, Device & Board Settings 3.1.1.1.2. Accessing Pre-Installed Design Examples 3.1.1.1.3. Accessing Online Design Examples 3.1.1.1.4. Accessing Downloaded Design Examples
3.1.1.1.3. Accessing Online Design Examples x
3.1.1.1.3.1. Internet Connectivity Options 3.1.1.1.3.2. Design Examples Options
3.2. Viewing Basic Project Information x
3.2.1. Using the Compilation Dashboard 3.2.2. Viewing Project Reports 3.2.3. Viewing Project Messages
3.2.3. Viewing Project Messages x
3.2.3.1. Viewing Synthesis Warning Messages 3.2.3.2. Suppressing Message Display 3.2.3.3. Promoting Critical Warnings to Errors
3.3. Intel® Quartus® Prime Project Contents x
3.3.1. Project File Best Practices
3.4. Managing Project Settings x
3.4.1. Optimizing Project Settings
3.4.1. Optimizing Project Settings x
3.4.1.1. Optimize Settings with Design Space Explorer II 3.4.1.2. Optimize Settings with Project Revisions 3.4.1.3. Back-Annotate Optimized Assignments
3.5. Managing Logic Design Files x
3.5.1. Including Design Libraries 3.5.2. Creating a Project Copy
3.8. Exporting Compilation Results x
3.8.1. Exporting a Version-Compatible Compilation Database 3.8.2. Importing a Version-Compatible Compilation Database 3.8.3. Creating a Design Partition 3.8.4. Exporting a Design Partition 3.8.5. Reusing a Design Partition 3.8.6. Viewing Quartus Database File Information 3.8.7. Clearing Compilation Results
3.8.6. Viewing Quartus Database File Information x
3.8.6.1. QDB File Attribute Types
3.9. Migrating Projects Across Operating Systems x
3.9.1. Migrating Design Files and Libraries 3.9.2. Design Library Migration Guidelines
3.9.1. Migrating Design Files and Libraries x
3.9.1.1. Use Relative Paths
3.10. Archiving Projects x
3.10.1. Manually Adding Files To Archives 3.10.2. Archiving Projects for Service Requests 3.10.3. Archiving Projects for External Revision Control 3.10.4. Creating Database-Only Archives
3.10.3. Archiving Projects for External Revision Control x
3.10.3.1. Project Files to Include In External Revision Control
3.11. Command-Line Interface x
3.11.1. Project Revision Commands 3.11.2. Project Archive Commands 3.11.3. Project Database Commands
3.11.3. Project Database Commands x
3.11.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
4. Design Planning x
4.1. Design Planning 4.2. Create a Design Specification and Test Plan 4.3. Plan for the Target Device or Board 4.4. Plan for Intellectual Property Cores 4.5. Plan for Standard Interfaces 4.6. Plan for Device Programming 4.7. Plan for Device Power Consumption 4.8. Plan for Interface I/O Pins 4.9. Plan for other EDA Tools 4.10. Plan for On-Chip Debugging Tools 4.11. Plan HDL Coding Styles 4.12. Plan for Hierarchical and Team-Based Designs 4.13. Design Planning Revision History
4.3. Plan for the Target Device or Board x
4.3.1. Device Migration Planning
4.9. Plan for other EDA Tools x
4.9.1. Third-Party Synthesis Tools 4.9.2. Third-Party Simulation Tools
4.11. Plan HDL Coding Styles x
4.11.1. Design Recommendations 4.11.2. Recommended HDL Coding Styles 4.11.3. Managing Metastability
4.12. Plan for Hierarchical and Team-Based Designs x
4.12.1. Flat Compilation without Design Partitions
5. Introduction to Intel® FPGA IP Cores x
5.1. IP Catalog and Parameter Editor 5.2. Installing and Licensing Intel® FPGA IP Cores 5.3. IP General Settings 5.4. Adding IP to IP Catalog 5.5. Best Practices for Intel® FPGA IP 5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.8. Scripting IP Core Generation 5.9. Modifying an IP Variation 5.10. Upgrading IP Cores 5.11. Simulating Intel® FPGA IP Cores 5.12. Generating Simulation Files for Platform Designer Systems and IP Variants 5.13. Synthesizing IP Cores in Other EDA Tools 5.14. Instantiating IP Cores in HDL 5.15. Support for the IEEE 1735 Encryption Standard 5.16. Introduction to Intel FPGA IP Cores Revision History
5.1. IP Catalog and Parameter Editor x
5.1.1. The Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
5.2.1. Intel® FPGA IP Evaluation Mode x
5.2.1.1. Intel FPGA IP Versioning 5.2.1.2. Checking the IP License Status
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
5.6.1. Applying Preset Parameters for Specific Applications 5.6.2. Customizing IP Presets
5.6.1. Applying Preset Parameters for Specific Applications x
5.6.1.1. Viewing, Applying, and Deleting IP Presets
5.6.2. Customizing IP Presets x
5.6.2.1. Defining Preset Pin Assignments
5.6.2.1. Defining Preset Pin Assignments x
5.6.2.1.1. Defining Preset Pin Assignments in Pin Assignments Tab 5.6.2.1.2. Defining Preset Pin Assignments in a Pin File
5.10. Upgrading IP Cores x
5.10.1. Upgrading IP Cores at Command-Line 5.10.2. Migrating IP Cores to a Different Device 5.10.3. Troubleshooting IP or Platform Designer System Upgrade
5.11. Simulating Intel® FPGA IP Cores x
5.11.1. Generating IP Simulation Files 5.11.2. Scripting IP Simulation
5.11.2. Scripting IP Simulation x
5.11.2.1. Generating a Combined Simulator Setup Script
5.14. Instantiating IP Cores in HDL x
5.14.1. Example Top-Level Verilog HDL Module 5.14.2. Example Top-Level VHDL Module
6. Migrating to Intel® Quartus® Prime Pro Edition x
6.1. Keep Pro Edition Project Files Separate 6.2. Upgrade Project Assignments and Constraints 6.3. Upgrade IP Cores and Platform Designer Systems 6.4. Upgrade Non-Compliant Design RTL 6.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
6.2. Upgrade Project Assignments and Constraints x
6.2.1. Modify Entity Name Assignments 6.2.2. Resolve Timing Constraint Entity Names 6.2.3. Verify Generated Node Name Assignments 6.2.4. Replace Logic Lock (Standard) Regions 6.2.5. Modify Signal Tap Logic Analyzer Files 6.2.6. Remove References to .qip Files 6.2.7. Remove Unsupported Feature Assignments
6.2.4. Replace Logic Lock (Standard) Regions x
6.2.4.1. Logic Lock Region Assignment Examples
6.4. Upgrade Non-Compliant Design RTL x
6.4.1. Verify Verilog Compilation Unit 6.4.2. Update Entity Auto-Discovery 6.4.3. Ensure Distinct VHDL Namespace for Each Library 6.4.4. Remove Unsupported Parameter Passing 6.4.5. Remove Unsized Constant from WYSIWYG Instantiation 6.4.6. Remove Non-Standard Pragmas 6.4.7. Declare Objects Before Initial Values 6.4.8. Confine SystemVerilog Features to SystemVerilog Files 6.4.9. Avoid Assignment Mixing in Always Blocks 6.4.10. Avoid Unconnected, Non-Existent Ports 6.4.11. Avoid Illegal Parameter Ranges 6.4.12. Update Verilog HDL and VHDL Type Mapping
6.4.1. Verify Verilog Compilation Unit x
6.4.1.1. Verilog HDL Configuration Instantiation
1. Answers to Top FAQs
2. Introduction to Intel® Quartus® Prime Pro Edition
3. Managing Intel® Quartus® Prime Projects
4. Design Planning
5. Introduction to Intel® FPGA IP Cores
6. Migrating to Intel® Quartus® Prime Pro Edition
7. Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides

4.13. Design Planning Revision History

Document Version Intel® Quartus® Prime Version Changes
2023.06.26 23.2
  • Updated Power Analyzer Settings screenshot for new settings name.
2023.04.03 23.1
  • Updated product family name to "Intel Agilex 7."
2022.12.12 22.4
  • Updated Plan for the Target Device or Board topic for board-aware features.
2022.06.20 22.2
  • Removed obsolete Simultaneous Switching Noise Analysis topic from this basic discussion.
2022.03.28 22.1
  • Added information about Power and Thermal Calculator in Plan for Device Power Consumption.
2021.10.04 21.3
  • Added support for Questa* Intel® FPGA Edition simulator.
  • Removed support for ModelSim - Intel FPGA Edition simulator.
2018.09.24 18.1.0
  • Moved information about specifying the target board to "Specifying the Target Device or Board" in Managing Projects chapter.
  • Retitled "Creating Design Specifications" to "Create a Design Specification and Test Plan."
  • Retitled "Selecting Intellectual Property Cores" to "Plan for Intellectual Property Cores."
  • Retitled "Using Standard Interfaces" to "Plan for Standard Interfaces." Corrected references to Platform Designer.
  • Retitled "Device Selection" to "Plan for the Target Device." Updated this content to correct Platform Designer names.
  • Moved "Setting Pin Assignments" to Managing Projects chapter as "Generating Pin Assignments for a Target Board."
  • Retitled "Estimating Power" to "Plan for Device Power Consumption." Reorganized this topic into sections for EPE and Power Analyzer.
  • Added link to "Simulator Support, Third-Party Simulation User Guide
  • Retitled "Planning for Device Programming or Configuration" to "Plan for Device Programming"
  • Retitled "Selecting Third-Party EDA Tools" to "Plan for other EDA Tools."
  • Retitled "Planning for On-Chip Debugging Tools" to "Plan for On-Chip Debugging Tools."
  • Retitled Design Planning with the Intel Quartus Prime Software to Design Planning
2018.05.07 18.0 Initial release as separate chapter of Getting Started User Guide.
Date Version Changes
2017.11.06 17.1.0
  • Changed instances of OpenCore Plus to Intel® FPGA IP Evaluation Mode.
  • Changed instances of Qsys to Platform Designer (Standard)
2017.05.08 17.0.0
  • Removed mentions to Integrated Synthesis.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.03 16.0.0 Added information about Development Kit selection.
2015.11.02 15.1.0
  • Added references to Interface Planning chapter.
  • Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0 Remove support for Early Timing Estimate feature.
2014.06.30 14.0.0 Updated document format.
November 2013 13.1.0 Removed HardCopy device information.
November, 2012 12.1.0 Update for changes to early pin planning feature
June 2012 12.0.0 Editorial update.
November 2011 11.0.1 Template update.
May 2011 11.0.0
  • Added link to System Design with Qsys in “Creating Design Specifications” on page 1–2
  • Updated “Simultaneous Switching Noise Analysis” on page 1–8
  • Updated “Planning for On-Chip Debugging Tools” on page 1–10
  • Removed information from “Planning Design Partitions and Floorplan Location Assignments” on page 1–15
December 2010 10.1.0
  • Changed to new document template
  • Updated “System Design and Standard Interfaces” on page 1–3 to include information about the Qsys system integration tool
  • Added link to the Product Selector in “Device Selection” on page 1–3
  • Converted information into new table (Table 1–1) in “Planning for On-Chip Debugging Options” on page 1–10
  • Simplified description of incremental compilation usages in “Incremental Compilation with Design Partitions” on page 1–14
  • Added information about the Rapid Recompile option in “Flat Compilation Flow with No Design Partitions” on page 1–14
  • Removed details and linked to Intel® Quartus® Prime Help in “Fast Synthesis and Early Timing Estimation” on page 1–16
July 2010 10.0.0
  • Added new section “System Design” on page 1–3
  • Removed details about debugging tools from “Planning for On-Chip Debugging Options” on page 1–10 and referred to other handbook chapters for more information
  • Updated information on recommended design flows in “Incremental Compilation with Design Partitions” on page 1–14 and removed “Single-Project Versus Multiple-Project Incremental Flows” heading
  • Merged the “Planning Design Partitions” section with the “Creating a Design Floorplan” section. Changed heading title to “Planning Design Partitions and Floorplan Location Assignments” on page 1–15
  • Removed “Creating a Design Floorplan” section
  • Removed “Referenced Documents” section
  • Minor updates throughout chapter
November 2009 9.1.0
  • Added details to “Creating Design Specifications” on page 1–2
  • Added details to “Intellectual Property Selection” on page 1–2
  • Updated information on “Device Selection” on page 1–3
  • Added reference to “Device Migration Planning” on page 1–4
  • Removed information from “Planning for Device Programming or Configuration” on page 1–4
  • Added details to “Early Power Estimation” on page 1–5
  • Updated information on “Early Pin Planning and I/O Analysis” on page 1–6
  • Updated information on “Creating a Top-Level Design File for I/O Analysis” on page 1–8
  • Added new “Simultaneous Switching Noise Analysis” section
  • Updated information on “Synthesis Tools” on page 1–9
  • Updated information on “Simulation Tools” on page 1–9
  • Updated information on “Planning for On-Chip Debugging Options” on page 1–10
  • Added new “Managing Metastability” section
  • Changed heading title “Top-Down Versus Bottom-Up Incremental Flows” to “Single-Project Versus Multiple-Project Incremental Flows”
  • Updated information on “Creating a Design Floorplan” on page 1–18
  • Removed information from “Fast Synthesis and Early Timing Estimation” on page 1–18
March 2009 9.0.0
  • No change to content
November 2008 8.1.0
  • Changed to 8-1/2 x 11 page size. No change to content.
May 2008 8.0.0
  • Organization changes
  • Added “Creating Design Specifications” section
  • Added reference to new details in the In-System Design Debugging section of volume 3
  • Added more details to the “Design Practices and HDL Coding Styles” section
  • Added references to the new Best Practices for Incremental Compilation and Floorplan Assignments chapter
  • Added reference to the Intel® Quartus® Prime Language Templates
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