Visible to Intel only — GUID: uaz1668636874357
Ixiasoft
3.1. Creating a New FPGA Design Project
3.2. Viewing Basic Project Information
3.3. Intel® Quartus® Prime Project Contents
3.4. Managing Project Settings
3.5. Managing Logic Design Files
3.6. Managing Timing Constraints
3.7. Integrating Other EDA Tools
3.8. Exporting Compilation Results
3.9. Migrating Projects Across Operating Systems
3.10. Archiving Projects
3.11. Command-Line Interface
3.12. Managing Projects Revision History
3.8.1. Exporting a Version-Compatible Compilation Database
3.8.2. Importing a Version-Compatible Compilation Database
3.8.3. Creating a Design Partition
3.8.4. Exporting a Design Partition
3.8.5. Reusing a Design Partition
3.8.6. Viewing Quartus Database File Information
3.8.7. Clearing Compilation Results
4.1. Design Planning
4.2. Create a Design Specification and Test Plan
4.3. Plan for the Target Device or Board
4.4. Plan for Intellectual Property Cores
4.5. Plan for Standard Interfaces
4.6. Plan for Device Programming
4.7. Plan for Device Power Consumption
4.8. Plan for Interface I/O Pins
4.9. Plan for other EDA Tools
4.10. Plan for On-Chip Debugging Tools
4.11. Plan HDL Coding Styles
4.12. Plan for Hierarchical and Team-Based Designs
4.13. Design Planning Revision History
5.1. IP Catalog and Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores
5.3. IP General Settings
5.4. Adding IP to IP Catalog
5.5. Best Practices for Intel® FPGA IP
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
5.8. Scripting IP Core Generation
5.9. Modifying an IP Variation
5.10. Upgrading IP Cores
5.11. Simulating Intel® FPGA IP Cores
5.12. Generating Simulation Files for Platform Designer Systems and IP Variants
5.13. Synthesizing IP Cores in Other EDA Tools
5.14. Instantiating IP Cores in HDL
5.15. Support for the IEEE 1735 Encryption Standard
5.16. Introduction to Intel FPGA IP Cores Revision History
6.2.1. Modify Entity Name Assignments
6.2.2. Resolve Timing Constraint Entity Names
6.2.3. Verify Generated Node Name Assignments
6.2.4. Replace Logic Lock (Standard) Regions
6.2.5. Modify Signal Tap Logic Analyzer Files
6.2.6. Remove References to .qip Files
6.2.7. Remove Unsupported Feature Assignments
6.4.1. Verify Verilog Compilation Unit
6.4.2. Update Entity Auto-Discovery
6.4.3. Ensure Distinct VHDL Namespace for Each Library
6.4.4. Remove Unsupported Parameter Passing
6.4.5. Remove Unsized Constant from WYSIWYG Instantiation
6.4.6. Remove Non-Standard Pragmas
6.4.7. Declare Objects Before Initial Values
6.4.8. Confine SystemVerilog Features to SystemVerilog Files
6.4.9. Avoid Assignment Mixing in Always Blocks
6.4.10. Avoid Unconnected, Non-Existent Ports
6.4.11. Avoid Illegal Parameter Ranges
6.4.12. Update Verilog HDL and VHDL Type Mapping
Visible to Intel only — GUID: uaz1668636874357
Ixiasoft
3.1.1.1.4. Accessing Downloaded Design Examples
You can create a new project from a design example that you have previously downloaded. Download a design example .par file from an online repository (such as the Intel FPGA Design Store) into your working directory. Designs that you create yourself and store in a local drive also appear as downloaded examples.
To create a new project based on downloaded design examples, follow these steps:
- Download a design example, as Accessing Online Design Examples describes.
Figure 11. Open Example Project Icon on Home Page
- Click the Open Example Project icon on the Intel® Quartus® Prime Pro Edition Home page. The Design Example page of the New Project Wizard opens.
- For What is the working directory for this project?, specify the directory location to store your project files.
- Under Find Options, specify the following settings. Refer to Family, Device & Board Settings.
- In Load from, select Downloaded design examples.
- In Family, Intel Quartus Prime version, and Development kit fields select the values to match your target design and board.
- In the design example list, select the design that you want to deploy.
Figure 12. Downloaded Intel Agilex® 7 I/O PLL Reconfiguration Design
- Click Next, and then click Finish. The design extracts to the working directory and opens in the Intel® Quartus® Prime software.