Visible to Intel only — GUID: svm1478794843390
Ixiasoft
Visible to Intel only — GUID: svm1478794843390
Ixiasoft
A.3.3. Verification Statistics Report
The verification statistics report becomes available after you simulate your component.
- The data presented in the verification statistics report might be dependent on the input values to the component from the test bench.
- The verification statistics report only reports the component loop initiation interval (II) values and throughput for enqueued invocations. For more details about enqueued invocations, refer to High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls.
The following example verification statistics report is for a component dut that has been run once as a simple function call and 100 times as an enqueued invocation:
For components that use explicit streams, such as ihc::stream_in<> or ihc::stream_out<>, the verification statistics report also provides the throughput for each individual stream, as shown in the details pane:
View the simulation waveform by following the instructions in Debugging during Verification.