5.1. The High-Level Design Reports
The High-Level Design Reports are a group of reports and viewers that you can use to help optimize your design by reviewing the statistics and visualizations that the reports provide.
Access the High-Level Design Reports by using a web browser to open the report.html file found in the <result>.prj/reports folder created when you compile your component to RTL.
Use the tutorials provided with the Intel® HLS Compiler to view examples of the reports and learn how to use the reports and viewers to help optimize and refine your component design.
For details about using the reports to help optimize your design, review Reviewing the High-Level Design Reports (report.html).
In some cases, information in the reports and viewers are estimates and might not match the results from compiling your design with Quartus® Prime software. However, compiling your component using the Quartus® Prime software might take several hours. In contrast, the Intel® HLS Compiler can generate the High Level Design Report in minutes for most designs.
Tip: Compiling your component using the Quartus® Prime Pro Edition software might take several hours. In contrast, the Intel® HLS Compiler Pro Edition can generate the High Level Design Reports in minutes for most designs.
The reports are divided into the following categories:
- The report under Summary gives you a quick overview of the results of compiling your design including a summary of each component in your design and a summary of the estimated resources that each component in your design uses.
- The viewers under Views provide different views into the structure, interfaces, datapaths, and computation flows in your component. These views can help identify bottlenecks in your design.
- The reports under Throughput Analysis help you analyze loops and provide key performance metrics on component blocks.
- The reports under Area Analysis provide a detailed breakdown of the estimated FPGA area usage. They also provide feedback on key hardware features such as private memory configuration.
Important: Do not use the estimated area usage for final resource utilization planning. For a more accurate estimate of area usages, synthesize your component with Quartus® Prime.
| Category | Report or Viewer Name | Description |
|---|---|---|
| Summary | Summary | The Summary Report gives you a quick overview of the results of compiling your design including a summary of each component in your design and a summary of the estimated resources that each component in your design uses. The Functions section shows you the short names generated for overloaded and templated functions in your hardware design by the Intel® HLS Compiler to prevent name collisions. These short names are used in other parts of the High Level Design Report. Other sections of the summary contain information only after you compile your design with Quartus® Prime software. |
| Views | System Viewer | The System Viewer is an interactive view of your system that allows you to review information such as the sizes and types of loads and stores, stalls, and latencies. Clicking on different entries in the hierarchical graph list displays different views of your design. |
| Function Memory Viewer | The Function Memory Viewer shows you the memory system that the Intel® HLS Compiler generated for your component. Use the Function Memory Viewer to help you identify data movement bottlenecks in your component design. | |
| Schedule Viewer | The Schedule Viewer shows the estimated start and ending clock cycle for functions, blocks, clusters, and individual instructions in your design. | |
| Throughput Analysis | Loop Analysis | The Loop Analysis Report shows the loop optimization strategies either applied by the compiler or through the various loop pragmas available. The report also provides key performance metrics on all blocks including any target II, scheduled fMAX, block II, and maximum interleaving iterations. You can use this report to help you with the following tasks:
Important: The scheduled fMAX that this report displays is not an accurate estimate of the fMAX that your design can achieve. Synthesize your component with Quartus® Prime to ensure that your design meets your performance requirements. You might also find that you can lower your scheduled fMAX target to save FPGA area utilization.
|
| Loop Viewer (alpha) | The Loop Viewer shows you the behavior of loops in your component and task functions as a color-coded Gantt chart. | |
| Verification Statistics | For each component that the testbench calls, the verification statistics report provides information such as the number and type of invocations, latency, initiation interval, and throughput. This report is available only after you simulate your component. |
|
| Area Analysis | Area Analysis of System | This report provides a detailed breakdown of the estimated FPGA area usage of your design. It also provides information about key hardware features such as private memory configuration. The Quartus Fit... sections are empty or hidden until you compile your design with Quartus® Prime software. The estimated area usage information correlates with, but does not necessarily match, the resource usage results from the Quartus® Prime software. Use the estimated area usage to identify parts of the design with large area overhead. You can also use the estimates to compare area usage between different designs. Do not use the estimated area usage information for final resource utilization planning. Synthesize your component with Quartus® Prime to determine accurate area usage information for final resource utilization planning. |
| Area Analysis of Source | This report is deprecated and might be removed in a future release. Use the Area Analysis of System report instead. |