Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
1. Intel® High Level Synthesis Compiler Pro Edition User Guide x
1.1. Discontinuation of the Intel® HLS Compiler
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

2.1. High Level Synthesis Design Flow

The Intel® High Level Synthesis (HLS) Compiler helps speed your IP development by letting you compile your IP component C++ code to different targets, depending on where you are in your IP development cycle.
The typical design flow when you use the Intel® HLS Compiler Pro Edition consists of the following stages:
  1. Creating your component and testbench.

    You can write a complete C++ application that contains both your component code and your testbench code.

    For details, see Creating a High-Level Synthesis Component and Testbench.

  2. Verify the functionality of your component algorithm and testbench.

    Verify the functionality by compiling your design to an x86-64 executable and running the executable. For details, see Verifying the Functionality of Your Design.

  3. Optimize and refine the FPGA performance of your component.

    Optimize the FPGA performance of your component by compiling your design to an FPGA target and reviewing the high-level design report to see where you can optimize your component. This step generates RTL code for your component. For details, see Optimizing and Refining Your Component.

    After initial optimizations, you can see where to further refine your component by simulating it. For details, see Verifying Your IP with Simulation.

  4. Synthesize your component with Quartus® Prime.

    For details, see Synthesize your Component IP with Quartus Prime Pro Edition.

    Synthesizing your component generates accurate quality-of-results (QoR) metrics like FPGA area utilization and fMAX.

  5. Integrate your IP into a system with Quartus® Prime or Platform Designer (formerly Qsys).

    For details, see Integrating your IP into a System.

The following flowchart shows a coarse-grained progression through the stages of a typical Intel® High Level Synthesis (HLS) Compiler design flow.
Figure 1. Overview of Procedure for Synthesizing IP for Intel® FPGA Products

For an example of the Intel® HLS Compiler design flow, watch the HLS Walkthrough series at the Intel FPGA channel on YouTube or complete the full-design tutorial found in <quartus_installdir>/hls/examples/tutorials/usability.

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