3.8.6. MIPI CSI-2 Receiver
The Intel® MAX® 10 FPGA 10M50 Evaluation Kit supports MIPI CSI-2 receiver D-PHY to both Leopard Imaging OV10640 and UDOO OV5640 modules. The OV10640 module includes one MIPI clock channel and four MIPI data channels, while the OV5640 module has one MIPI clock channel and two MIPI data channels.
To interface MIPI CSI-2 D-PHY compliant I/O, the Intel® MAX® 10 10M50 evaluation kit uses one 2.5V LVDS signal pair to support high-speed mode and one 1.2V HSTL signal pair to support low-power mode for each MIPI clock or data lane.
Source | Schematic Signal Name | Device/Pin Number | I/O Standard | Description |
---|---|---|---|---|
J2 (Cable needed to interface OV10640 module) |
P/N: 52559-3652 | |||
J2.11 | OV10640_CLK_HS_P | Intel® MAX® 10/P11 | 2.5V LVDS | Differential input clock (high speed, positive terminal) |
J2.12 | OV10640_CLK_HS_N | Intel® MAX® 10/R11 | 2.5V LVDS | Differential input clock (high speed, negative terminal) |
J2.11 | OV10640_CLK_LP_P | Intel® MAX® 10/T21 | 1.2V HSTL | Differential input clock (low power, positive terminal |
J2.12 | OV10640_CLK_LP_N | Intel® MAX® 10/T22 | 1.2V HSTL | Differential input clock (low power, negative terminal |
J2.8 | OV10640_DATA_HS_P1 | Intel® MAX® 10/AA20 | 2.5V LVDS | Differential input data Lane1 (high speed, positive terminal) |
J2.9 | OV10640_DATA_HS_N1 | Intel® MAX® 10/AB21 | 2.5V LVDS | Differential input data Lane1 (high speed,negative terminal) |
J2.8 | OV10640_DATA_LP_P1 | Intel® MAX® 10/P21 | 1.2V HSTL | Differential input data Lane1 (low power,positive terminal) |
J2.9 | OV10640_DATA_LP_N1 | Intel® MAX® 10/N22 | 1.2V HSTL | Differential input data Lane1 (low power, negative terminal) |
J2.14 | OV10640_DATA_HS_P2 | Intel® MAX® 10/AB20 | 2.5V LVDS | Differential input data Lane2 (high speed, positive terminal) |
J2.15 | OV10640_DATA_HS_N2 | Intel® MAX® 10/AB19 | 2.5V LVDS | Differential input data Lane2 (high speed, negative terminal |
J2.14 | OV10640_DATA_LP_P2 | Intel® MAX® 10/V21 | 1.2V HSTL | Differential input data Lane2 (low power,positive terminal) |
J2.15 | OV10640_DATA_LP_N2 | Intel® MAX® 10/V22 | 1.2V HSTL | Differential input data Lane2 (low power, negative terminal |
J2.17 | OV10640_DATA_HS_P3 | Intel® MAX® 10/AB18 | 2.5V LVDS | Differential input data Lane3 (high speed, positive terminal) |
J2.18 | OV10640_DATA_HS_N3 | Intel® MAX® 10/AB17 | 2.5V LVDS | Differential input data Lane3 (high speed, negative terminal) |
J2.17 | OV10640_DATA_LP_P3 | Intel® MAX® 10/Y22 | 1.2V HSTL | Differential input data Lane3 (low power, positive terminal) |
J2.18 | OV0640_DATA_LP_N3 | Intel® MAX® 10/W22 | 1.2V HSTL | Differential input data Lane3 (low power, negative terminal) |
J2.20 | OV10640_DATA_HS_P4 | Intel® MAX® 10/AA16 | 2.5V LVDS | Differential input data Lane4 (high speed, positive terminal) |
J2.21 | OV10640_DATA_HS_N4 | Intel® MAX® 10/AB16 | 2.5V LVDS | Differential input data Lane4 (high speed, negative terminal) |
J2.20 | OV10640_DATA_LP_P4 | Intel® MAX® 10/AA21 | 1.2V HSTL | Differential input data Lane4 (low power, positive terminal) |
J2.21 | OV10640_DATA_LP_N4 | Intel® MAX® 10/AA22 | 1.2V HSTL | Differential input data Lane4 (low power, negative terminal) |
J2.23 | OV10640_CMOS_RST | Intel® MAX® 10/P4 | 1.8V LVCMOS | Reset/Power down |
J2.24 | OV10640_CMOS_SDATA | Intel® MAX® 10/N8 | 1.8V LVCMOS | Control Bus Data |
J2.25 | OV10640_CMOS_SCLK | Intel® MAX® 10/P5 | 1.8V LVCMOS | Control Bus Clock |
J2.26 | OV10640_24MHz | Intel® MAX® 10/N5 | 1.8V LVCMOS | 24 MHz Reference Clock Output |
J2.27 | OV10640_GYRO_INT | Intel® MAX® 10/N9 | 1.8V LVCMOS | Gyroscope Programmable Interrupt |
J2.28 | OV10640_G_RDY | Intel® MAX® 10/R4 | 1.8V LVCMOS | Gyroscope Data Ready |
J2.31 | OV10640_XM_INT1 | Intel® MAX® 10/R7 | 1.8V LVCMOS | Accelerometer and magnetic sensor interrupt 1 |
J2.30 | OV10640_XM_INT2 | Intel® MAX® 10/R5 | 1.8V LVCMOS | Accelerometer and magnetic sensor interrupt 2 |
J2.32 | OV10640_FSIN | Intel® MAX® 10/P8 | 1.8V LVCMOS | Frame sync input |
J2.4, J2.5 | 1.8V | ---- | 1.8V | 1.8V |
J2.1, J2.2, J2.3 | 3.3V | ---- | 3.3V | 3.3V |
J2.6, J2.7, J2.10, J2.13, J2.16, J2.19, J2.22, J2.29, J2.33, J2.34 | GND | ---- | GND | GND |
Source | Schematic Signal Name | Device/Pin Number | I/O Standard | Description |
---|---|---|---|---|
J3 (Cable needed to interface OV5640 module) |
Wurth Electronics 68711614522 | |||
J3.6 | OV5640_CLK_HS_P | Intel® MAX® 10/V10 | 2.5V LVDS | Differential input clock (high speed, positive terminal) |
J3.5 | OV5640_CLK_HS_N | Intel® MAX® 10/V9 | 2.5V LVDS | Differential input clock (high speed, negative terminal) |
J3.6 | OV5640_CLK_LP_P | Intel® MAX® 10/R15 | 1.2V HSTL | Differential input clock (low power, positive terminal) |
J3.5 | OV5640_CLK_LP_N | Intel® MAX® 10/R14 | 1.2V HSTL | Differential input clock (high speed, positive terminal) |
J3.9 | OV5640_DATA_HS_P1 | Intel® MAX® 10/AB13 | 2.5V LVDS | Differential input data Lane1 (high speed,positive terminal) |
J3.8 | OV5640_DATA_HS_N1 | Intel® MAX® 10/AB12 | 2.5V LVDS | Differential input data Lane1 (high speed,negative terminal) |
J3.9 | OV5640_DATA_LP_P1 | Intel® MAX® 10/W19 | 1.2V HSTL | Differential input data Lane1 (low power,positive terminal) |
J3.8 | OV5640_DATA_LP_N1 | Intel® MAX® 10/W20 | 1.2V HSTL | Differential input data Lane1 (low power,negative terminal) |
J3.2 | OV5640_DATA_HS_P2 | Intel® MAX® 10/AB11 | 2.5V LVDS | Differential input data Lane2 (high speed,positive terminal) |
J3.1 | OV5640_DATA_HS_N2 | Intel® MAX® 10/AB10 | 2.5V LVDS | Differential input data Lane2 (high speed,negative terminal) |
J3.2 | OV5640_DATA_LP_P2 | Intel® MAX® 10/P15 | 1.2V HSTL | Differential input data Lane2 (low power,positive terminal) |
J3.1 | OV5640_DATA_LP_N2 | Intel® MAX® 10/P14 | 1.2V HSTL | Differential input data Lane2 (low power,negative terminal) |
J3.13 | OV5640_SDC | Intel® MAX® 10/M3 | 3.3V LVCMOS | Control Bus Clock |
J3.14 | OV5640_SDA | Intel® MAX® 10/L1 | 3.3V LVCMOS | Control Bus Data |
J3.12 | OV5640_CLK24MHz | Clock Generator / U14.18 | 3.3V LVCMOS | System Input Clock |
J3.15 | OV5640_CAM_RESETB | Intel® MAX® 10/M4 | 3.3V LVCMOS | Reset |
J3.11 | OV5640_PWRON | Intel® MAX® 10/L2 | 3.3V LVCMOS | Power Down |
J3.16 | 3.3V | ---- | 3.3V | 3.3V |
J3.3, J3.4, J3.7, J3.10 | GND | ---- | GND | GND |
To download MIPI reference designs for this Evaluation Kit, please contact your local Intel PSG (formerly Altera) sales team for assistance or check the FPGA Design Store.