Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

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ID 683447
Date 1/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components A. Additional Information
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Intel® Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. On-Board Oscillators 3.7.2. Off-Board Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Document Revision History for the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide A.2. Safety and Regulatory Information A.3. Compliance Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
A. Additional Information

3.6. General User Input/Output

User-defined I/O signal names, FPGA pin numbers, and I/O standards for the Intel® MAX® 10 FPGA 10M50 Evaluation Board.
Table 11.  User-Defined Push Button Signal Names
Board Reference Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard
S1 USER_PB0 R20 1.2 V
S2 USER_PB1 Y20 1.2 V
S3 USER_PB2 Y21 1.2 V
S4 USER_PB3 U20 1.2 V
Table 12.  User-Defined DIP Switch Schematic Signal Names
Board Reference Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard
SW1.1 USER_DIPSW0 R18 1.2 V
SW1.2 USER_DIPSW1 T19 1.2 V
SW1.3 USER_DIPSW2 T18 1.2 V
SW1.4 USER_DIPSW3 U19 1.2 V
SW2.1 USER_DIPSW4 G4 3.3 V
SW2.2 USER_DIPSW5 F5 3.3 V
Table 13.  User LED Schematic Signal Names
Board Reference Signal Name Color Intel® MAX® 10 FPGA Pin Number I/O Standard
D3 USER_LED0 Green C3 3.3 V
D4 USER_LED1 Green C4 3.3 V
D5 USER_LED2 Green C5 3.3 V
D6 USER_LED3 Green D5 3.3 V
D7 USER_LED4 Green C7 3.3 V

Table 14.  User Defined I/O Through-Hole Vias
Board Reference Schematic Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard Note 1 Description
J12.1 2.5V Power ---- ----

Power Supply Connector for J12
J12.2 2.5V Power ---- ----

Power Supply Connector for J12
J12.3 USER_CLKIN_IO_P K22

DIFFIO_RX_R40P or CLK3P

Single-ended clock input
J12.4 USER_LVDS_P2 Y17

DIFFIO_TX_RX_B43P, High Speed

LVDS User I/O_2. Note 1
J12.5 USER_CLKIN_IO_N K21

DIFFIO_RX_R40N or CLK3N

Dual purpose pin. Either single-ended User I/O or single-ended clock input
J12.6 USER_LVDS_N2 AA17

DIFFIO_TX_RX_B43N, High Speed

LVDS User I/O_2. Note 1
J12.7 GND ---- ----

Ground Reference for this group of I/Os
J12.8 GND ---- ----

Ground Reference for this group of I/Os
J12.9 USER_LVDS_P0 AA10

DIFFIO_TX_RX_B22P, High Speed

LVDS User I/O_0. Note 1
J12.10 USER_LVDS_P3 Y14

DIFFIO_TX_RX_B37P, High Speed

LVDS User I/O_3. Note 1
J12.11 USER_LVDS_N0 Y10

DIFFIO_TX_RX_B22N, High Speed

LVDS User I/O_0. Note 1
J12.12 USER_LVDS_N3 Y13

DIFFIO_TX_RX_B37N, High Speed

LVDS User I/O_3. Note 1
J12.13 GND ---- ----

Ground Reference for this group of I/Os
J12.14 GND ---- ----

Ground Reference for this group of I/Os
J12.15 USER_LVDS_P1 W8

DIFFIO_TX_RX_B13p, High Speed

LVDS User I/O_1. Note 1
J12.16 CLKOUT_LVDS_P V17

DIFFIO_TX_RX_B57P or PLL_B_CLKOUTP

Dual purpose pin. Either User I/O or Clock output ref. for this group of LVDS channels

J12.17 USER_LVDS_N1 W7

DIFFIO_TX_RX_B13n, High Speed

LVDS User I/O_1. Note 1
J12.18 CLKOUT_LVDS_N W17

DIFFIO_TX_RX_B57N or PLL_B_CLKOUTN

Dual purpose pin. Either User I/O or Clock output ref. for this group of LVDS channels

J12.19 GND ---- ----

Ground Reference for this group of I/Os
J12.20 GND ---- ----

Ground Reference for this group of I/Os
J13.1 2.5V Power ---- ----

Power Supply for Connector J13
J13.2 2.5V Power ---- ----

Power Supply for Connector J13
J13.3 USER_LVDS_P5 V8

DIFFIO_TX_RX_B7p, High Speed

LVDS User I/O_5. Note 1
J13.4 USER_LVDS_P8 AA7

DIFFIO_TX_RX_B16p, High Speed

LVDS User I/O_8. Note 1
J13.5 USER_LVDS_N5 V7

DIFFIO_TX_RX_B7n, High Speed

LVDS User I/O_5. Note 1
J13.6 USER_LVDS_N8 AA6

DIFFIO_TX_RX_B16n, High Speed

LVDS User I/O_8. Note 1
J13.7 GND ---- ----

Ground Reference for this group of I/Os
J13.8 GND ---- ----

Ground Reference for this group of I/Os
J13.9 USER_LVDS_P6 W6

DIFFIO_TX_RX_B1p, High Speed

LVDS User I/O_6. Note 1
J13.10 USER_LVDS_P4 W10

DIFFIO_TX_RX_B11p, High Speed

LVDS User I/O_4. Note 1
J13.11 USER_LVDS_N6 W5

DIFFIO_TX_RX_B1n, High Speed

LVDS User I/O_6. Note 1
J13.12 USER_LVDS_N4 W9

DIFFIO_TX_RX_B11n, High Speed

LVDS User I/O_4. Note 1
J13.13 GND ---- ----

Ground Reference for this group of I/Os
J13.14 GND ---- ----

Ground Reference for this group of I/Os
J13.15 USER_LVDS_P7 W3

DIFFIO_TX_RX_B5p, High Speed

LVDS User I/O_7. Note 1
J13.16 NC ---- ----

Not Connected
J13.17 USER_LVDS_N7 W4

DIFFIO_TX_RX_B5n, High Speed

LVDS User I/O_7. Note 1
J13.18 NC ---- ----

Not Connected
J13.19 GND ---- ----

Ground Reference for this group of I/Os
J13.20 GND ---- ----

Ground Reference for this group of I/Os
J14.1 USER_IO0 A17

DIFFIO_RX_T10n, High Speed

User I/O_0
J14.2 USER_IO5 A19

DIFFIO_RX_T8n, High Speed

User I/O_5
J14.3 USER_IO1 B19

DIFFIO_RX_T6n, High Speed

User I/O_1
J14.4 USER_IO6 A20

DIFFIO_RX_T8p, High Speed

User I/O_6
J14.5 3.3V power ---- ----

Power Supply for Connector J14
J14.6 3.3V power ---- ----

Power Supply for Connector J14
J14.7 USER_IO2 E16

DIFFIO_RX_T1p, High Speed

User I/O_2
J14.8 USER_IO7 C18

DIFFIO_RX_T7p, High Speed

User I/O_7
J14.9 USER_IO3 C19

DIFFIO_RX_T6n, High Speed

User I/O_3
J14.10 USER_IO8 C17

DIFFIO_RX_T2n, High Speed

User I/O_8
J14.11 GND ---- ----

Ground Reference for this group of I/Os
J14.12 GND ---- ----

Ground Reference for this group of I/Os
J14.13 USER_IO4 F16

DIFFIO_RX_T5p, High Speed

User I/O_4
J14.14 USER_IO9 D17

DIFFIO_RX_T2p, High Speed

User I/O_9
Note: 1. Termination resistors are required to be installed by the user for proper high speed LVDS I/O use.
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