Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Overview of the Intel® FPGA Power and Thermal Calculator 3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 4. Intel® FPGA Power and Thermal Calculator Graphical User Interface 5. Intel® FPGA Power and Thermal Calculator Pages 6. Factors Affecting the Accuracy of the Intel® FPGA PTC 7. Intel® FPGA Power and Thermal Calculator User Guide Archive 8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
2. Overview of the Intel® FPGA Power and Thermal Calculator x
2.1. Accessing the Intel FPGA Power and Thermal Calculators 2.2. Intel® FPGA PTC Power Model Status 2.3. Definitions of Power Terms Used in this Document
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
3.1. Estimating Power Before Starting the FPGA Design 3.2. Estimating Power While Creating the FPGA Design 3.3. Estimating Power After Completing the FPGA Design 3.4. Estimating Power for Dual-Core Devices
3.2. Estimating Power While Creating the FPGA Design x
3.2.1. Importing a .qptc File Generated in the Intel® Quartus® Prime Power Analyzer
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
4.1. Intel® FPGA PTC Select Family Dialog Box 4.2. Intel® FPGA PTC Primary GUI Components 4.3. Intel® FPGA PTC - IP Wizard 4.4. Intel® FPGA PTC Searchable Drop-Down Lists 4.5. Deleting Rows from Data Entry Pages 4.6. Finding Resources Using the Find Dialog Box
4.2. Intel® FPGA PTC Primary GUI Components x
4.2.1. Intel® FPGA PTC Data Entry Pages 4.2.2. Intel® FPGA PTC Design Hierarchy 4.2.3. Intel® FPGA PTC IP Power Summary 4.2.4. Intel® FPGA PTC Field Types 4.2.5. Intel® FPGA PTC Data Entry Error Messages
4.2.2. Intel® FPGA PTC Design Hierarchy x
4.2.2.1. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 4.2.2.2. Entering Hierarchy Information Into the Intel® FPGA PTC 4.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC 4.2.2.4. Bulk Editing Hierarchies in the Intel FPGA PTC
4.2.4. Intel® FPGA PTC Field Types x
4.2.4.1. Intel® FPGA PTC Input Field Dependencies
5. Intel® FPGA Power and Thermal Calculator Pages x
5.1. Intel® FPGA PTC - Power Summary/Navigation 5.2. Intel® FPGA PTC - Common Page Elements 5.3. Intel® FPGA PTC - Main Page 5.4. Intel® FPGA PTC - Logic Page 5.5. Intel® FPGA PTC - RAM Page 5.6. Intel® FPGA PTC - DSP Page 5.7. Intel® FPGA PTC - Clock Page 5.8. Intel® FPGA PTC - PLL Page 5.9. Intel® FPGA PTC - I/O Page 5.10. Intel® FPGA PTC - Transceiver Page 5.11. Intel® FPGA PTC - HPS Page 5.12. Intel® FPGA PTC - Crypto Page 5.13. Intel FPGA PTC - NOC Page 5.14. Intel® FPGA PTC - HBM Page 5.15. Intel® FPGA PTC - Thermal Page 5.16. Intel® FPGA PTC - Report Page
5.3. Intel® FPGA PTC - Main Page x
5.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
5.10. Intel® FPGA PTC - Transceiver Page x
5.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
6. Factors Affecting the Accuracy of the Intel® FPGA PTC x
6.1. Toggle Rate 6.2. I/O Bank Allocation
1. Answers to Top FAQs
2. Overview of the Intel® FPGA Power and Thermal Calculator
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface
5. Intel® FPGA Power and Thermal Calculator Pages
6. Factors Affecting the Accuracy of the Intel® FPGA PTC
7. Intel® FPGA Power and Thermal Calculator User Guide Archive
8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

5.7. Intel® FPGA PTC - Clock Page

Each row in the Clock page of the Intel® FPGA Power and Thermal Calculator (PTC) represents a clock network or a separate clock domain in the design.

Intel Agilex® 7 and Intel® Stratix® 10 devices support global, regional, and periphery clock networks. The Intel® FPGA PTC does not distinguish between global or regional clocks because the difference in power is not significant.

Figure 40. Clock Page of the Intel® FPGA PTC


Table 15.  Clock Page Information
Column Heading Description
Entity Name Enter a name for the clock entity in this column. This is an optional value.
Full Hierarchy Name Enter the full hierarchy name for the entity represented in this row. Delimit levels of hierarchy with a vertical bar ( | ) symbol, for example: a|b|c.
Clock Freq (MHz) Enter the frequency of the clock domain. This value is limited by the maximum frequency specification for the device family.
Note:

When you import a design from the Intel® Quartus® Prime software, some imported clocks may have a frequency of 0 MHz, due to either of the following reasons:

  • The Intel® Quartus® Prime software did not have sufficient information to determine clock frequency due to incomplete clock constraints.
  • Clock resources were used to route a reset signal, which toggles infrequently, so its frequency is reported as 0 MHz.
Total Fanout

Enter the total number of flipflops, hyper-registers, RAMs, digital signal processing (DSP) blocks, and I/O pins fed by this clock.

The number of resources driven by every global clock and regional clock signal is reported in the Fan-out column of the Intel® Quartus® Prime Compilation Report. In the Compilation Report, select Fitter and click Place Stage. Select Global & Other Fast Signals Summary and observe the Fan-out value.

Note: Power consumed by Intel® Stratix® 10 MLAB clocks is accounted for in the RAM page; therefore, clock fanout on this page does not include any MLABs driven by this clock domain, for Intel® Stratix® 10 devices. For Intel Agilex® 7 devices, MLAB is included in the fanout.
Global Enable % Enter the average percentage of time that the entire clock tree is enabled. Each global clock buffer has an enable signal that you can use to dynamically shut down the entire clock tree.
Local Enable %

Enter the average percentage of time that clock enable is high for destination flipflops.

Local clock enables for flipflops in ALMs are promoted to LAB-wide signals. When a given flipflop is disabled, the LAB-wide clock is disabled, cutting clock power and the power for down-stream logic. This page models only the impact on clock tree power.

Utilization Factor

Represents the impact of the clock network configuration on power.

Characteristics that have a large impact on power and are captured by this factor include the following:

  • Whether the network is widely spread out
  • Whether the fanout is small or large
  • The clock settings within each LAB

The default value for this field is typical; the actual value varies between clocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Intel® Quartus® Prime software after compiling your design, because the Intel® Quartus® Prime software has access to detailed placement information.

In the absence of an Intel® Quartus® Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals.

You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design.

Power (W) Indicates the total power dissipation due to clock distribution (in W).
User Comments Enter any comments. This is an optional entry.
Note: The Domain column which appeared in earlier versions of the PTC, is now the Full Hierarchy Name column. If you import a design file from a previous version of the PTC, any Domain entries will now appear in the Full Hierarchy Name column.

For more information about the clock networks of Intel Agilex® 7 devices, refer to the Intel Agilex® 7 Clocking and PLL User Guide.

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