Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.3.7. Programming the FPGA with the Canny Edge Reference Design

Ensure the ARM processor completes its boot process before programming the FPGA.
  1. Load the FPGA image from the Quartus II programmer: Tools > Programmer.
  2. Program the file top.sof
  3. To program the FPGA from the ARM processor:
    Note: Do not program the FPGA from the ARM processor if the ARM processor already has an FPGA image loaded.
    1. Ensure all MSEL dip switches are in the ON position.
    2. Ensure the program burn_fpga is available.
    3. Ensure the FPGA image canny_fpga.rbf is available. 
      root@socfpga:~/altera# ./burn_fpga canny_fpga.rbf
Burning FPGA image file canny_fpga.rbf
Ensure all MSEL DIP switches are ON
13685+1 records in
13685+1 records out
FPGA image burned from SD card!
ARM-FPGA bridges are enabled!
      FPGA LED 0 and 1 are now ON to indicate that the FPGA is running.
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