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Ixiasoft
1.1. About Canny Edge Detection
1.2. About the Canny Edge Detection Reference Design
1.3. Getting Started with the Canny Edge Reference Design
1.4. Canny Edge Detection Reference Design Block Description
1.5. Stream-to-Memory Conversion
1.6. Latency and Throughput
1.7. Canny Edge Reference Design Resource Usage
1.3.1. Hardware and Software Requirements
1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design
1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image
1.3.4. Canny Edge Reference Design Initial Startup Problems
1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design
1.3.6. Capturing the Pixel Stream
1.3.7. Programming the FPGA with the Canny Edge Reference Design
1.3.8. Initializing the ARM Processor
Visible to Intel only — GUID: dmi1420814354925
Ixiasoft
1.4.1. Greyscale Conversion
Edge detection algorithms operate on one color channel. The video input has three color channels, so the design converts it to grayscale.
The design uses the NTSC standard color space to convert. The design avoids using complex floating-point hardware, which limits fMAX performance and introduces clock cycle latency if pipelining is used to increase fmax performance. The design uses bit-slice method to simplify floating point calculations where precision is not required. However, this method can only be used if the coefficients are constant.
Figure 2. Greyscale