Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.2. About the Canny Edge Detection Reference Design

The Altera® Canny edge detection reference design targets a Cyclone® V SoC, which contains an Altera Cyclone V FPGA and a dual core ARM® Cortex A9 hard processor system (HPS). This design partitions the Canny edge detection across the FPGA and ARM processor, using the FPGA as a hardware accelerator. The ARM processor runs the software algorithms, which are easier to execute in software than in hardware.

Using the Cyclone V SoC boosts performance and lowers power consumption. The flexibility of the reference design allows you to develop other custom applications around it.

FPGAs offer the most optimal solution. FPGAs use stream-based processing that produces an output pixel as each input pixel arrives. This approach is suitable for common image pre-processing operations such as two dimensional convolution and monochrome conversion. The reference design's custom hardware implementation results in minimal logic utilization and very little on-chip FPGA memory usage, which gives a fast and power-efficient design architecture. The design can chain the stream-based processing blocks together. Internal FPGA voltages for RTL blocks are small as compared to I/O voltages, which gives power savings.

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