Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.4.2. Gaussian Blurring

Canny edge detection is very sensitive to noise. The design uses a two dimensional Gaussian filter to blur the grayscale output image

A Gaussian filter is a low pass filter that attenuates high frequency noise. By convolving the image matrix with the Gaussian kernel, the design smudges the image as each individual output pixel is the weighted Gaussian average of its surrounding pixels (spatial weighted averaging). To obtain the discrete Gaussian kernel coefficients, the design determines the kernel size and chooses the appropriate standard deviation from the continuous 2D Gaussian equation. Implementing 2D convolution in hardware is similar to that of 1D convolution. Both cases use a tapped delay line. However the 2D case needs to delay an entire video line to access the previous matrix row entry using FIFO buffers. For previous column entries, the design uses register delay lines. Hence, a FIFO buffer implements row delays; registers implement column delays.

Figure 3. Gaussian Blurring
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