Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.5.3. Frame Buffering

The Canny edge reference design uses a triple buffering pointer to buffer video frames in the ARM processor. This pointer swap mechanism prevents unnecessary copying from the input frame buffer to a processing buffer and from the processing buffer to the output frame buffer. The pointer swap mechanism has 3 buffers: Input, Processing and Output.

During a pointer swap, the design swaps the input buffer pointer with the processing buffer. The samples in the new processing buffer are ready for image processing. Likewise, the design swaps the processing buffer pointer with the output buffer. Then the processed video frame is ready for the design to output. The design swaps the output buffer pointer with the input buffer.

To ensure the design does not swap the processing buffer before it processes an image frame, the pointer change occurs only when image processing on a video frame is complete. The ARM processor informs the mSGDMA of a frame process completion via the FPGA-ARM AXI connection bus. To ensure the input buffer is filled, the swap must also occur only on the start of a new video frame. Processing a video frame can take longer than 1/60 seconds because of algorithmic complexity and the amount of pixel data in one frame, so the design may drop video frames, decreasing the output frame rate.

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