Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.6. Latency and Throughput

When each input pixel enters the five-block pipeline, the Canny edge reference design produces an output pixel in steady state, which is a throughput of one pixel per clk_dvi.
The design shows a total latency of 6 line and 14 pixel delays, because the Gaussian, Sobel and nonmaximal support blocks each have two line and two pixel delays. The remaining eight pixel delays are:
  • The synchronous monochrome block
  • The five-stage register pipeline for the 45 degree angle approximation block
  • The presence of input and output (I/O) registers that latch the incoming and outgoing pixel data and control signals.

The edge linking block gives a minimum output latency of one video frame.

The most efficient edge-linked video throughput is measured to be 15 to 30 frames per second (fps) depending on the input video resolution and the input video content. 60 fps is not achieved as the design drops some frames as edge linking cannot be completed within 1/60 seconds.

Video latency and throughput analysis are important for the human visual perception. High video latency looks like the video output lags behind the video input. If video throughput is low, the output video appears jerky. Pixel and line delays are almost impossible to discern because of the sheer size of a video frame. Generally, the output frame latency must not be more than 50 ms (three frame lag). For smooth video rendering, the output video throughput limit is 15 fps. The design meets these human perceptual visual limits, so the output video rendering appears to be instantaneous. However, safety critical video analytics, for example, emergency car braking, might require faster response times.

Level Two Title