Intel® MAX™ 10 Embedded Memory User Guide

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ID 683431
Date 5/05/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
2. Intel® MAX® 10 Embedded Memory Architecture and Features x
2.1. Intel® MAX® 10 Embedded Memory General Features 2.2. Intel® MAX® 10 Embedded Memory Operation Modes 2.3. Intel® MAX® 10 Embedded Memory Clock Modes 2.4. Intel® MAX® 10 Embedded Memory Configurations
2.1. Intel® MAX® 10 Embedded Memory General Features x
2.1.1. Control Signals 2.1.2. Parity Bit 2.1.3. Read Enable 2.1.4. Read-During-Write 2.1.5. Byte Enable 2.1.6. Packed Mode Support 2.1.7. Address Clock Enable Support 2.1.8. Asynchronous Clear
2.1.5. Byte Enable x
2.1.5.1. Byte Enable Controls 2.1.5.2. Data Byte Output 2.1.5.3. RAM Blocks Operations
2.1.7. Address Clock Enable Support x
2.1.7.1. Address Clock Enable During Read Cycle Waveform 2.1.7.2. Address Clock Enable During Write Cycle Waveform
2.1.8. Asynchronous Clear x
2.1.8.1. Resetting Registers in M9K Blocks
2.2. Intel® MAX® 10 Embedded Memory Operation Modes x
2.2.1. Supported Memory Operation Modes
2.3. Intel® MAX® 10 Embedded Memory Clock Modes x
2.3.1. Asynchronous Clear in Clock Modes 2.3.2. Output Read Data in Simultaneous Read and Write 2.3.3. Independent Clock Enables in Clock Modes
2.4. Intel® MAX® 10 Embedded Memory Configurations x
2.4.1. Port Width Configurations 2.4.2. Memory Configurations for Single-Port Modes 2.4.3. Memory Configurations for Dual-Port Modes 2.4.4. Maximum Block Depth Configuration
3. Intel® MAX® 10 Embedded Memory Design Consideration x
3.1. Implement External Conflict Resolution 3.2. Customize Read-During-Write Behavior 3.3. Consider Power-Up State and Memory Initialization 3.4. Control Clocking to Reduce Power Consumption 3.5. Selecting Read-During-Write Output Choices
3.2. Customize Read-During-Write Behavior x
3.2.1. Same-Port Read-During-Write Mode 3.2.2. Mixed-Port Read-During-Write Mode
3.2.2. Mixed-Port Read-During-Write Mode x
3.2.2.1. Mixed-Port Read-During-Write Operation with Dual Clocks
4. RAM: 1-Port IP Core References x
4.1. RAM: 1-Port IP Core Signals For Intel® MAX® 10 Devices 4.2. RAM: 1-Port IP Core Parameters For Intel® MAX® 10 Devices
5. RAM: 2-PORT IP Core References x
5.1. RAM: 2-Ports IP Core Signals (Simple Dual-Port RAM) For Intel® MAX® 10 Devices 5.2. RAM: 2-Port IP Core Signals (True Dual-Port RAM) for Intel® MAX® 10 Devices 5.3. RAM: 2-Port IP Core Parameters for Intel® MAX® 10 Devices
6. ROM: 1-PORT IP Core References x
6.1. ROM: 1-PORT IP Core Signals For Intel® MAX® 10 Devices 6.2. ROM: 1-PORT IP Core Parameters for Intel® MAX® 10 Devices
7. ROM: 2-PORT IP Core References x
7.1. ROM: 2-PORT IP Core Signals for Intel® MAX® 10 Devices 7.2. ROM: 2-Port IP Core Parameters For Intel® MAX® 10 Devices
8. FIFO IP Core References x
8.1. FIFO IP Core Signals for Intel® MAX® 10 Devices 8.2. FIFO IP Core Parameters for Intel® MAX® 10 Devices 8.3. FIFO Functional Timing Requirements 8.4. SCFIFO ALMOST_EMPTY Functional Timing
9. Shift Register (RAM-based) IP Core References x
9.1. Shift Register (RAM-based) IP Core Signals for Intel® MAX® 10 Devices 9.2. Shift Register (RAM-based) IP Core Parameters for Intel® MAX® 10 Devices
10. ALTMEMMULT IP Core References x
10.1. ALTMEMMULT IP Core Signals for Intel® MAX® 10 Devices 10.2. ALTMEMMULT IP Core Parameters for Intel® MAX® 10 Devices
1. Intel® MAX® 10 Embedded Memory Overview
2. Intel® MAX® 10 Embedded Memory Architecture and Features
3. Intel® MAX® 10 Embedded Memory Design Consideration
4. RAM: 1-Port IP Core References
5. RAM: 2-PORT IP Core References
6. ROM: 1-PORT IP Core References
7. ROM: 2-PORT IP Core References
8. FIFO IP Core References
9. Shift Register (RAM-based) IP Core References
10. ALTMEMMULT IP Core References
11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide

2.2.1. Supported Memory Operation Modes

Table 3.  Supported Memory Operation Modes in the M9K Embedded Memory Blocks
Memory Operation Mode Related IP Core Description
Single-port RAM RAM: 1-PORT IP Core

Single-port mode supports non-simultaneous read and write operations from a single address.

Use the read enable port to control the RAM output ports behavior during a write operation:

  • To show either the new data being written or the old data at that address, activate the read enable (rden) during a write operation.
  • To retain the previous values that are held during the most recent active read enable, perform the write operation with the read enable port deasserted.
Simple dual-port RAM RAM: 2-PORT IP Core

You can simultaneously perform one read and one write operations to different locations where the write operation happens on Port A and the read operation happens on Port B.

In this memory mode, the M9K memory blocks support separate wren and rden signals. To save power, keep rden signal low (inactive) when not reading.

True dual-port RAM RAM: 2-PORT IP Core

You can perform any combination of two port operations:

  • Two reads, two writes, or;
  • One read and one write at two different clock frequencies.

In this memory mode, the M9K memory blocks support separate wren and rden signals. To save power, keep rden signal low (inactive) when not reading.

Single-port ROM ROM: 1-PORT IP Core Only one address port is available for read operation.

You can use the memory blocks as a ROM.

  • Initialize the ROM contents of the memory blocks using a .mif or .hex file.
  • The address lines of the ROM are registered.
  • The outputs can be registered or unregistered.
  • The ROM read operation is identical to the read operation in the single-port RAM configuration.
Dual-port ROM ROM: 2-PORT IP Core

The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation.

You can use the memory blocks as a ROM.

  • Initialize the ROM contents of the memory blocks using a .mif or .hex file.
  • The address lines of the ROM are registered.
  • The outputs can be registered or unregistered.
  • The ROM read operation is identical to the read operation in the single-port RAM configuration.
Shift-register Shift Register (RAM-based) IP Core

You can use the memory blocks as a shift-register block to save logic cells and routing resources.

The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). The size of the shift register must be less than or equal to the maximum number of memory bits (9,216 bits). The size of (w × n) must be less than or equal to the maximum of width of the blocks (36 bits).

You can cascade memory blocks to implement larger shift registers.

FIFO FIFO IP Core

You can use the memory blocks as FIFO buffers.

  • Use the FIFO IP core in single clock FIFO (SCFIFO) mode and dual clock FIFO (DCFIFO) mode to implement single- and dual-clock FIFO buffers in your design.
  • Use dual clock FIFO buffers when transferring data from one clock domain to another clock domain.
  • The M9K memory blocks do not support simultaneous read and write from an empty FIFO buffer.
Memory-based multiplier ALTMEMMULT IP Core You can use the memory blocks as a memory-based multiplier.
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